Semiconductor integrated circuit having current leakage...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

Reexamination Certificate

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Details

C326S119000, C326S121000

Reexamination Certificate

active

11238975

ABSTRACT:
A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor. The power gating to the CMOS inverter is performed by feedback of the output signal and the complementary input signal, with the result that current leakage reduction through the CMOS controlled inverter is achieved. A self leakage reduction with power gating transistors is applicable to another type of logic gates such as NAND, NOR and Exclusive-OR, AND, OR.

REFERENCES:
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patent: 5751651 (1998-05-01), Ooishi
patent: 6515521 (2003-02-01), Kono et al.
patent: 6696865 (2004-02-01), Horiguchi et al.
patent: 2006/0012397 (2006-01-01), Cooper
patent: 2006/0055424 (2006-03-01), Park et al.
Horiguchi et al., “Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI's”,IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1131-1135.

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