Semiconductor integrated circuit having clock synchronous...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses

Reexamination Certificate

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C713S600000, C327S141000, C365S233100

Reexamination Certificate

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06839859

ABSTRACT:
A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock non-synchronous type circuit. The read data is latched in selected one of N latch circuits. A latch circuit is selected on the basis of a control signal instead of a clock signal. The control signal represents that read data is output from the clock non-synchronous type circuit, and hence a latch circuit is always selected after read data is output.

REFERENCES:
patent: 4615017 (1986-09-01), Finlay et al.
patent: 4669100 (1987-05-01), Slotboom et al.
patent: 5502720 (1996-03-01), Muramatsu
patent: 5796660 (1998-08-01), Toda
patent: 6292428 (2001-09-01), Tomita et al.
Ryoichi Nishimachi et al.; 1992, 3, 26 Japanese Patent Publication (Kokoku) No. 1992-17565.
Kiroshi Adachi; 1992, 6, 23. Japanese Patent Publication (Kokoku) No. 1992-38016.

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