Semiconductor integrated circuit having bonding optional...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C327S313000, C326S016000

Reexamination Certificate

active

07076705

ABSTRACT:
Current consumption of an input unit with respect to a bonding option pad is reduced, and erroneous operation of a circuit connected to this bonding option pad is prevented. A boundary scan test circuit is selectively set to an operable or disabled state by a control gate according to a signal from a function set circuit that sets the operation mode according to a potential of a bonding pad. By particularly controlling the operable and disabled state of an input circuit located at the first stage of the test circuit, power consumption can be reduced and erroneous operation while the test circuit is disabled is prevented.

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patent: 5767694 (1998-06-01), Ogata
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patent: 02-302987 (1990-12-01), None
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patent: 06-069425 (1994-03-01), None
“BGA Packages, Gaining Popularity in U.S.; Make High Density Mounting of High Pin Count LSIs Easy”, A. Fukuda, Nikkei Electronics, Feb. 14, 1994, pp. 59-73.
M5M5V1132FP, GP-6, -7, -8, -7L, -8L, Mitsubishi's Product Data Sheet Mar. 24, 1997, pp. 1-14.
Gallup et al (Testability features of the 68040: IEEE, Sep. 14, 1990).

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