Semiconductor integrated circuit having a clock skew test circui

Details Semiconductor integrated circuit having a clock skew test circui Semiconductor integrated circuit having a clock skew test circui

1995-06-26

1996-11-26

Westin, Edward P.

Electronic digital logic circuitry

With test facilitating feature

371 1, 371 221, 327292, H03K 1900

Patent

active

055789382

ABSTRACT:
A semiconductor integrated circuit has a test circuit capable of accurately measuring the clock skew of a clock signal in an LSI. The test circuit includes first and second flip flops driven by the clock signal in a maximum clock skew to receive a test signal. The test signal is supplied through a test signal input pin to data inputs of the first and second flip flops in the same signal delay. The outputs of the first and second flip flops are connected to the inputs of an exclusive OR gate. The test signal is varied stepwise by an amount at a time corresponding to the resolution of an LSI tester, and the output of the exclusive OR gate is detected to measure the clock skew in the clock signal.

REFERENCES:
patent: 5235566 (1993-08-01), Merrill
patent: 5337321 (1994-08-01), Ozaki
patent: 5430394 (1995-07-01), McMinn et al.
patent: 5479127 (1995-12-01), Bui
patent: 5498983 (1996-03-01), Schoellkopf

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