Semiconductor integrated circuit for generating clock signals

Details Semiconductor integrated circuit for generating clock signals Semiconductor integrated circuit for generating clock signals

2011-08-30

2011-08-30

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S226000, C365S194000

Reexamination Certificate

active

08009486

ABSTRACT:
A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

REFERENCES:
patent: 6545941 (2003-04-01), Kato et al.
patent: 6985041 (2006-01-01), Wong et al.
patent: 7320082 (2008-01-01), Tsern et al.
patent: 2005/0195674 (2005-09-01), Jang
patent: 2008/0303494 (2008-12-01), Nakakubo
patent: 1020040018850 (2004-03-01), None
patent: 1020040066511 (2004-07-01), None

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