Semiconductor integrated circuit evaluation system

Details Semiconductor integrated circuit evaluation system Semiconductor integrated circuit evaluation system

1998-10-23

2000-05-09

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36518907, 371 271, 371274, G11C 700

Patent

active

060612835

ABSTRACT:
A semiconductor integrated circuit evaluation system for evaluating, at high speed, functions of a device under test and a test pattern for testing the device under test without using an actual tester or designed device. The evaluation system includes a test pattern file for storing a test pattern to be applied to a device for testing the device under test, a first memory for storing tester event information by receiving a predetermined amount of test pattern from the test pattern file, a first FIFO (first-in-first-out) for receiving a predetermined amount of the tester event information from the first memory and extracting the tester event information in the order of receiving the same, a second memory for storing device event information by receiving a predetermined amount of event information resulted from logic simulation of the device under test based on design data of the device produced through a computer aided design process, a second FIFO for receiving a predetermined amount of the device event information from the second memory and extracting the device event information in the order of receiving the same, a comparator for comparing the event information from the first FIFO and the second FIFO, and means for generating a comparison result from the comparator.

REFERENCES:
patent: 5140686 (1992-08-01), Cox et al.
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5815513 (1998-09-01), Hiraide

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