Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-12
2003-03-25
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
06539511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, it relates to a semiconductor integrated circuit device with a test circuit. More specifically, the present invention relates to a semiconductor integrated circuit device which can be readily subjected to a DC test (direct current test) with no influence on the internal structure.
2. Description of the Background Art
A semiconductor integrated circuit device is subjected to various tests on functions, performance and electric characteristics of the product after fabrication, on the level of a single chip and on the level of a board having the chip mounted thereon. For example, “ULSI Design Technique” issued by the Institute of Electronics, Information and Communication Engineers describes such tests performed on the chip level and the board level.
A DC (direct current) characteristic test is performed as one test for testing electric characteristics of a single chip. Items tested in the DC characteristic test include potentials VIL and VIH when “0” or “1” is externally input, a leakage current of an input pin terminal, a potential VOL or VOH when “0” or “1” is output, and a leakage current (standby leakage current) in a high impedance (Hi-Z) state.
On the other hand, a boundary scan test (JTAG (joint test action group) test) standardized in IEEE (IEEE Std. 1149.1) is performed on the chip mounted on a board. The boundary scan test is performed by sequentially scanning all external input/output pins of a semiconductor integrated circuit device for inputting/outputting test data to test the internal functions of the integrated circuit device (chip) and the board on which the chip is mounted. In JTAG test, shift registers are arranged in correspondence to input/output pin terminals and test data are serially transferred through the shift registers for testing connection in the integrated circuit device, connection between the pin terminals of the integrated circuit device and the board, and the like.
In such a BGA (hall grid array) package that pin terminals are arranged on the rear surface of the chip and cannot be externally observed after on-board assembly, contact failures of the pin terminals or the like can be readily tested by shifting test data with shift registers called boundary scan registers. Also even when the number of pin terminals increases and a pitch of the pins reduces below that of test probes for performing a test, the integrated circuit device can be readily tested. The JTAG test standard defines a boundary scan register connected to an input/output circuit, and an input/output control circuit of an input/output buffer (I/O buffer) respectively, and a control unit for controlling a test operation.
FIG. 43
schematically illustrates the overall structure of a conventional semiconductor integrated circuit device
1000
. Referring to
FIG. 43
, semiconductor integrated circuit device
1000
includes an input circuit
100
a
receiving an input signal supplied through an input terminal group
1001
and generating an internal input signal, an internal logic circuit
1000
b
performing a prescribed operation in accordance with the internal input signal supplied from input circuit
1000
a
, and an output circuit
1000
c
receiving an internal output signal from internal logic circuit
1000
b
for outputting to an output terminal group
1002
. Internal logic circuit
1000
b
may be a logic circuit performing a desired logical processing or a circuit for controlling an access to a memory or the like.
In a test operation for semiconductor integrated circuit device
1000
, input terminal group
1001
and output terminal group
1002
are coupled to a testing apparatus
1010
through an input signal bus
1003
and an output signal bus
1004
. Testing apparatus
1010
generates a test pattern in accordance with a predetermined test program for application to input terminal group
1001
of semiconductor integrated circuit device
1000
through input signal bus
1003
. Testing apparatus
1010
receives a signal supplied from output terminal group
1002
through output signal bus
1004
and compares the received signal with an expected value for determining whether or not internal logic circuit
1000
b
of the semiconductor integrated circuit device normally operates.
In a DC test operation, testing apparatus
1010
supplies a test pattern for setting the input terminal group
1001
and the output terminal group
1002
in states “0”, “1” and “Hi-Z”. As the test pattern supplied from the testing apparatus
1010
in DC test, a test pattern suitable for performing the DC test must be extracted from those previously prepared in testing apparatus
1010
. In this case, test patterns changing the states of all terminals included in input terminal group
1001
and output terminal group
1002
respectively must be previously prepared for selecting and applying an appropriate test pattern. However, logic implemented by internal logic circuit
1000
b
is so complicated that it is difficult to create test patterns changing the states of all terminals. When performing the DC test on semiconductor integrated circuit device
1000
singly, therefore, each terminal cannot be set in a desired state with the test pattern from testing apparatus
1010
and hence the DC test cannot be readily performed.
FIG. 44
illustrates the structure of another conventional semiconductor integrated circuit device
1100
. Referring to
FIG. 44
, semiconductor integrated circuit device
1100
includes a selector
1102
selecting one of an input signal supplied to an input terminal
1101
, a power supply voltage Vcc and a ground voltage Vss under the control of a test control circuit
1110
, an input buffer
1103
receiving a signal supplied through selector
1102
and generating an internal signal, an internal logic circuit
1104
performing prescribed processing in accordance with the internal signal from the input buffer
1103
, a selector
1105
selecting one of an output signal of internal logic circuit
1104
, power supply voltage Vcc and ground voltage Vss under the control of test control circuit
1110
, and an output buffer
1106
buffering a signal (voltage) supplied from selector
1105
and outputting the buffered signal (voltage) to an output terminal
1107
. Test control circuit
1110
determines the selection modes of selectors
1102
and
1105
in accordance with a test mode instruction signal &phgr;T supplied through a test mode signal input terminal
1108
.
The states of input buffer
1103
and output buffer
1106
can be set by setting connection paths of selectors
1102
and
1105
by the test control circuit
1110
, to perform a DC test. In this structure, however, selector
1102
must be provided between input buffer
1103
and input terminal
1101
, while selector
1105
must be provided between internal logic circuit
1104
and output buffer
1106
. The selectors
1102
and
1105
, which are provided on signal propagation paths, cause signal propagation delay, and hence the semiconductor integrated circuit device
1100
cannot be operated at a high speed.
Further, interconnection lines are required for transmitting control signals to selectors
1102
and
1105
to disadvantageously increase the areas occupied by interconnection lines, while the selectors
1102
and
1105
must be provided in correspondence to the input terminals and the output terminals respectively to disadvantageously increase the circuit scale and the area occupied by the chip.
In the structure of the semiconductor integrated circuit device shown in
FIG. 44
, therefore, the chip area is disadvantageously increased to impede high integrationization although the states of the buffers
1103
and
1106
are not required to be set by extracting a test pattern from a test program under the control of the external testing apparatus, but each terminal is readily set in a desired state.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor in
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tu Christine T.
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