Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-10-08
2004-03-02
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050
Reexamination Certificate
active
06700817
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device which comprises a data storage section, formed inside a chip, for storing desirable mode setting data corresponding to products of a plurality of types, redundancy data, and so on.
Examples of product types in a semiconductor integrated circuit device are
(1) a product type in which the layout of pads depends on a package such as TSOP (Thin Small Outline Package)/SOP (Small Outline Package), and the locations of pads to be used are switched,
(2) a product type in which parallel data have different bit lengths such as x4, x8, and x16, and the numbers of I/O blocks and sense amplifiers to be activated change in accordance with a bit length, and
(3) a product type in which addressing changes such that the top and bottom of an address for designating an irregular block are switched in an irregular-block product in a flash EEPROM.
In the semiconductor integrated circuit device having a plurality of different modes, the operation mode of the device must be determined by some method.
In general, either of the master slice or bonding option methods is conventionally selected in order to develop one mask set into the types of products having a plurality of different modes.
In the master slice method, different modes are switched by exchanging, e.g., A1 masks. This method is generally used in developing one mask set into a plurality of mode types.
On the other hand, the bonding option method uses an input signal from a dummy pad to select a different mode. A power supply voltage or ground potential is applied to the dummy pad to determine the mode of an integrated circuit by either potential.
A semiconductor integrated circuit device in which a plurality of product types are developed by the bonding option method is disclosed in, e.g., the following reference:
EUROPEAN PATENT Publication Number 0 476 282 A2 (lines 29-44, p. 10,
FIG. 1
n
and the like).
In the bonding option method, no plurality of masks need be prepared compared to the master slice method, and data need not be managed in correcting the mask.
In the master slice method, one product type requires one mask. Assume that four product types are simultaneously developed, and the product type is switched by A1 masks. If a given A1 mask must be corrected, four A1 masks must be corrected, resulting in high mask cost. If the number of times of correction is large, the correction contents may not be completely managed. All functions corresponding to the corrected masks must be checked, and the evaluation is cumbersome.
In the bonding option method, a power supply or ground potential is applied to a dummy pad for determining the contents of a device. Therefore, the dummy pad must be arranged between power supply pins or ground pins. Alternatively, the bonding option exclusively requires a pad connected to the power supply and a pad connected to the ground adjacent to the dummy pad. Since the bonding option method requires a large number of extra pads to lead to an increase in chip area, this method cannot cope with so many modes.
Semiconductor integrated circuit devices designed in consideration of the above technology and comprising data storage sections that store mode setting data corresponding to products of a plurality of types, are disclosed, for example, in the following publications:
Jpn. Pat. Appln. KOKAI Publication No. 2-116084 (the description between the fourteenth line of the lower left column of page 2 and the eleventh line of the lower right column of the same page, and FIG.
2
); and
Jpn. Pat. Appln. KOKAI Publication No. 6-243677 (the descriptions in paragraphs [0044] and [
0102
], and
FIG. 10
)
In the semiconductor integrated circuit device disclosed in each of these publications, mode setting data are stored in a nonvolatile transistor. Due to this feature, the semiconductor integrated circuit device enables one mask set to be developed into a plurality of product types, eliminates the need for extra pads, and does not therefore require an increased chip area.
The data storage section, which includes a nonvolatile transistor, stores mode setting data corresponding to products of a plurality of types. Accordingly, the data storage section requires very high reliability.
However, the two Japanese KOKAI publication No. 2-116084 and No. 6-243677 do not disclose any measures that can be taken to improve the reliability of the data storage section.
BRIEF SUMMARY OF THE INVENTION
A semiconductor integrated circuit device according to an aspect of the present invention comprises: a nonvolatile memory cell, a source of the nonvolatile memory cell receiving a ground potential, and a gate of the nonvolatile memory cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the nonvolatile memory cell, and a gate of the transistor receiving a second control signal; a load, the load being connected between a voltage supply line and a drain of the transistor; a latch circuit, an input of the latch circuit being connected to the drain of the transistor and a node of the load; and a controller, wherein the controller receives a third control signal generated upon detection of power-on and outputs the first control signal and the second control signal, a potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.
REFERENCES:
patent: 5032742 (1991-07-01), Zanders
patent: 5757714 (1998-05-01), Choi et al.
patent: 5828611 (1998-10-01), Kaneko et al.
patent: 5867047 (1999-02-01), Kraus
patent: 5917766 (1999-06-01), Tsuji et al.
patent: 6052313 (2000-04-01), Atsumi et al.
patent: 6188266 (2001-02-01), Shimoda
patent: 6320428 (2001-11-01), Atsumi et al.
patent: 6480426 (2002-11-01), Atsumi et al.
patent: 0476282 (1992-03-01), None
patent: 2-116084 (1990-04-01), None
patent: 6-243677 (1994-09-01), None
Atsumi Shigeru
Banba Hironori
Kuriyama Masao
Saito Hidetoshi
Taura Tadayuki
Kabushiki Kaisha Toshiba
Tran Andrew Q.
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