Semiconductor integrated circuit device with test circuit

Details Semiconductor integrated circuit device with test circuit Semiconductor integrated circuit device with test circuit

1999-11-08

2002-05-28

Tu, Christine T. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S819000, C714S704000

Reexamination Certificate

active

06397363

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a test circuit and a redundant circuit for a memory circuit, and having a function to supply information about the presence or absence of a fault and about fault remediableness.
2. Description of Related Art
One of conventional semiconductor integrated circuit devices including a test circuit and a redundant circuit is disclosed in Japanese patent application laid-open No. 8-94718 (1996).
FIG. 10
is circuit diagram showing a scan flip-flop for RAM test in a conventional semiconductor integrated circuit device disclosed in the foregoing Japanese patent application laid-open No. 8-94718 (1996). In
FIG. 10
, the reference numeral
100
designates a scan flip-flop (SFF),
101
designates a comparator for comparing data output from a RAM including a plurality of memory cells with a preset expected value, and for outputting a compared result.
FIG. 11
is a circuit diagram showing a RAM with a test circuit in a conventional semiconductor integrated circuit device. In
FIG. 11
, the reference numeral
111
designates a RAM consisting of a plurality of memory cells. Outputs DO<> of the RAM
111
are connected to five scan flip-flops (SFFs)
100
connected in series. The five scan flip-flops (SFFs)
100
connected in series constitute a scan path circuit for testing the RAM
111
.
FIG. 12
is a circuit diagram showing a conventional semiconductor integrated circuit device with a RAM
121
combined with a redundant circuit
122
. The RAM
121
is a 5-bit RAM with a test circuit consisting of the RAM
111
and the five scan flip-flops (SFFs)
100
connected in series to constitute a scan path circuit as shown in FIG.
11
. In
FIG. 12
, the reference numeral
123
designates a register for loading and storing the output data SO<i+1>−SO<i+4> from the scan flip-flops (SFFs)
100
. The RAM
121
of the semiconductor integrated circuit device with a test circuit supplies the register
123
with 5-bit data output signals SO<i>, SO<i+1>, SO<i+2>, SO<i+3> and SO<i+4>.
Next, the operation of the conventional device will be described.
First, a test operation will be described for the RAM
111
with five scan flip-flops (SFFS)
100
constituting the scan path circuit as shown in FIG.
11
.
Before carrying out the operation test of the RAM
111
, which is a memory circuit including a plurality of memory cells, that is, a plurality of bits, a control signal TM and a control signal SM are set at TM=0 and SM=1, and data “1” is shifted in from the SIDO terminal of the first scan flip-flop (SFF)
100
. For example, the five bit scan path circuit as shown in
FIG. 11
requires five clock pulses. As a result, the outputs of the scan flip-flops (SFFs)
100
are placed at SO<i>=1, SO<i+1>=1, SO<i+2>=1, SO<i+3>=1 and SO<i+4>=1.
Subsequently, a test of the entire addresses of the RAM
111
is performed with placing the control signals at TM=1 and SM=1. During writing and reading of the test data to and from the RAM
111
, expected values EXP and a comparison control signal CMP (compare when “1”) are controlled.
If a fault takes place in the RAM
111
while the comparison control signal CMP=1, the output DO<> of the RAM
111
associated with the fault will differ from its expected value EXP, and hence the output signal from the comparator
101
will be “0”. Thus, the output SO of the scan flip-flop (SFF) becomes “0” in synchronism with a clock signal T. For example, if a fault occurs in the bit DO<i+2> of the RAM
111
, the fault is detected at the scan flip-flop (SFF) <i+2>
100
corresponding to the bit, and the output SO<i+2> of the scan flip-flop (SFF) <i+2>
100
becomes “0”. In this case, the remaining scan flip-flops (SFFs)
100
maintain their outputs at “1”, and produces them as the outputs SO<i>, SO<i+1>, SO<i+3> and SO<i+4>.
After that, while the control signals are placed at TM=0 and SM=1, the test result is shifted out from the terminal SODO<i> of the final scan flip-flop (SFF)
100
.
Next, the operation will be described of the RAM
121
with a test circuit including a redundant circuit
122
. The semiconductor integrated circuit device as shown in
FIG. 12
includes the redundant circuit
122
in connection with the RAM
121
with the test circuit as shown in FIG.
11
. For example, if a bit fault is detected at the scan flip-flop (SFF) <i+2>
100
corresponding to the output DO<i+2> of the RAM
121
, the output SO<i+2> of that scan flip-flop (SFF)
100
becomes “0”. In this case, the remaining scan flip-flops (SFFs)
100
produce “1” as their outputs SO<i>, SO<i+1>, SO<i+3> and SO<i+4>.
Loading the outputs SO<i+1>−SO<i+4> from the scan flip-flops (SFFs)
100
, the register
123
produces “1”, “0”, “1” and “1” as its outputs G<i+1>−G<i+4>, respectively. Thus, the outputs of logic gates
1221
,
1222
and
1223
in the redundant circuit
122
will be F<i+3>=1, F<i+2>=0 and F<i+1>=0, respectively.
As a result, the output value DO<i+4>/Q<i+4> of the RAM
121
becomes the output value XDO<i+3> of the redundant circuit
122
. Likewise, DO<i+3>/Q<i+3> becomes XDO<i+2>, DO<i+1>/Q<i+1> becomes XDO<i+1> and DO<i>/Q<i>becomes XDO<i>, thus eliminating the output value DO<i+2> corresponding to the fault bit.
In much the same fashion, the input value XDI<i+3> to the redundant circuit
122
becomes the input value DI<i+4> to the RAM
121
. Likewise, XDI<i+2> becomes DI<i+3>, XDI<i+1> becomes DI<i+2> and DI<i+1>, and XDI<i> becomes DI<i>.
As a result, even if a bit error takes place in the memory cell corresponding to the output DO<i+2>, for example, the RAM
121
functions as a 4-bit input/output RAM because of a connecting/switching operation in the redundant circuit
122
. However, if a two or more bit fault takes place in the data outputs DO<> of the RAM
121
, a fault remedial processing using the foregoing redundant circuit
122
cannot be applied.
With such an arrangement, the foregoing conventional semiconductor integrated circuit device has a problem of taking a long time for carrying out the fault test of a plurality of memory cells constituting the semiconductor integrated circuit device. This is because to achieve the fault remedial processing, it is necessary to decide as to whether two or more pieces of fault information (value “0” in the foregoing example) are present in the test result shifted out from the SODO<i>, and this requires an external test device such as an LSI tester (not shown in the drawings) for making the decision.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of reducing the time required for the test for the presence or absence of a fault of memory cells and for the fault remediableness. This is implemented by making a comparison and decision within the semiconductor integrated circuit device as to whether any fault information is present or not in the plurality of memory cells in the semiconductor integrated circuit device, and by outputting comparison and decision result to facilitate a fault decision processing and fault remedial processing by an external test instrument like an LSI tester.
According to a first aspect of the present invention, there is provid

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