Semiconductor integrated circuit device with fault analysis...

Details Semiconductor integrated circuit device with fault analysis... Semiconductor integrated circuit device with fault analysis...

1999-12-09

2003-05-27

Decady, Albert (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S720000, C714S730000

Reexamination Certificate

active

06571364

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with fault analysis function capable of testing a memory circuit such as a RAM incorporated therein and then performing fault analysis operation in detail.
2. Description of the Related Art
A conventional test circuit for testing a memory circuit portion incorporated in a semiconductor integrated circuit device is disclosed, for instance, in U.S. Pat. No. 5,815,512 (corresponding to a Japanese laid open publication No. JP-A-8/94718).
FIG. 1
is a circuit diagram showing a scan flip flop to be used in the test of a memory circuit such as a RAM (Random Access Memory). In
FIG. 1
, the reference numbers
2
-
5
and
2
91
each designates a scan flip flop (SFF), and
292
denotes a comparator incorporated in the scan flip flop (SFF)
291
. This comparator
292
compares the output from a memory circuit D such as a RAM with an expected value EXP that has been prepared previously, and then outputs a comparison to the outside of the scan flip flop (SFF)
291
. The reference number
293
indicates a flip flop (FF) for temporarily storing the comparison result transferred from the comparator
292
.
FIG. 2
is a block diagram showing a RAM as a memory circuit and a conventional test circuit. In
FIG. 2
, the reference number
301
designates a RAM as a memory circuit,
291
denotes four scan flip flops connected in series that form a scan path to be used for a memory test operation of the RAM
301
. The scan flip flop
291
is the same as the scan flip flop shown in
FIG. 1
in configuration.
FIG. 3
is a diagram showing a configuration of the RAM
301
of 32 words and 4 bits as the object of test. In
FIG. 3
, the reference character WD designates a write-in driver circuit, SA denotes a sense amplifier, and
311
and
312
indicate a Y address decoder and a X address decoder, respectively. The reference number
313
designates each of column selectors, and
314
denotes each of memory cell groups G
0
to G
4
. Each memory cell group
314
has thirty-two memory cells
0
to
31
.
The reference character DI< > (DI<
0
> to DI<
3
>) designates input data signals that are input through data input terminals to the RAM
301
, and DO< > (DO<
0
> to DO<
3
>) denotes output data signals that are output to outside of the RAM
301
through data output terminals.
The reference number A< > (XA< > and YA< >) designates address signals that are input through address terminals to the RAM
301
, and WE denotes a write enable signal that is input through the write enable terminal.
In general, as shown in
FIG. 3
, each memory cell group corresponding to one bit data input/output is arranged in a two dimension arrangement (for example, in a 4×8 arrangement). Each of the memory cells in the memory cell group
314
in the RAM
301
shown in
FIG. 3
is selected by using the X address (XA<
2
>, XA<
1
> and XA<
0
>) and the Y address (YA<
1
> and YA<
2
>).
In each of the memory cell groups (G
0
to G
3
)
314
in the RAM
301
shown in
FIG. 3
comprises thirty-two memory cells (4×8=32). Each of the memory cells is selected by one of addresses 0 to 31. For example, when the address signals are XA<
2
>=1, XA<
1
>=0, XA<
0
>=1, and YA<
1
>=1 and YA<
0
>=0, the output X
5
in the X decoder
312
is activated to select the output Y
2
of each of the column selectors
313
. As a result, the memory cell addressed by the address
32
in each of the memory cell group
314
is selected.
Next, a description will be given of the test operation for the conventional example.
In the RAM
301
, the data output signals DO<
0
>, DO<
1
>, DO<
2
> and DO<
3
> of four bits that have been read from the memory cell groups (G
0
to G
3
)
314
are output to corresponding flip flops
291
in the scan path shown in
FIG. 2
, respectively.
Because the four scan flip flips (SFF)
291
in the conventional example shown in
FIG. 2
are connected in series, it takes four clocks to set the value 1 into all of the scan flip flops
291
in serial data transmission. As a result, the values of the output signals outputted from the scan flip flops
291
through the terminal SO becomes SO<
0
>=1, SO<
1
>=1, SO<
2
>=1 and SO<
3
>=1, respectively.
Next, both the control signals TM and SM are set to TM=1 and SM=1. In this situation, the test operation is executed by using all of the addresses of the RAM
301
. That is to say, expected values EXP and a comparison control signal CMP are properly controlled while executing the write-in operation and read-out operation for all of the memory cells in the RAM
301
by using the all of the addresses. For example, the comparison instruction to initiate the comparison operation is given to the comparator
292
under CMP=1. As a result, because the value obtained through the data output terminal DO< > from a defective memory cell in the RAM
301
is not equal to the expected value, the output of the comparator incorporated in the scan flip flop
291
(that corresponds to the comparator
292
shown in
FIG. 1
) becomes zero and the scan flip flop
291
corresponding to this comparator is reset to zero in synchronization with the clock signal T.
For example, when the scan flip flop (SFF<
2
>)
291
corresponding to the data output signal DO<
2
> from the memory cell in the RAM
301
detects a defective memory cell, the output signal from the scan flip flop (SFF<
2
>)
291
has the value of zero (SO<
2
>=0). Other outputs from other scan flip flops (SFF<
0
>, SFF<
1
>, and SFF<
3
>)
291
maintain the value of one (SO<
0
>=1, SO<
1
>=1, and SO<
3
>=1).
Next, both the control signals TM and SM are set to TM=0 and SM=1 and then test results SO<
0
> are shifted to the outside through the output terminal SO of the scan flip flop
291
in the final stage. When the test results are output serially, the output signal SO<
0
> becomes the serial output data SODO shown in FIG.
2
.
Because the conventional semiconductor integrated circuit has the configuration described above, the test results from the memory cell group G
3
are transferred to and then stored in the scan flip flop SFF<
3
>, the test results from the memory cell group G
2
are transferred to and then stored in the scan flip flop SFF<
2
>, the test results from the memory cell group G
1
are transferred to and then stored in the scan flip flop SFF<
1
>, and the test results from the memory cell group G
0
are transferred to and then stored in the scan flip flop SFF<
0
>.
Accordingly, it is difficult to diagnose and distinguish a kind of defect in the conventional semiconductor integrated circuit device, for example, the defect is whether a fault of a single bit in a memory cell, of a bit line, or of a word line.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a semiconductor integrated circuit device with fault analysis function capable of efficiently performing the test operation for a memory section such as a RAM, and of easily performing a fault analysis in detail.
In accordance with one aspect of the present invention, a semiconductor integrated circuit device with fault analysis function has a memory circuit, a scan path and a comparison control circuit. The memory circuit has a plurality of memory cells that are divided into a plurality of memory cell groups in which data stored in the memory cells addressed by address signals are read and then output. The scan path has a plurality of scan flip flops placed corresponding to the plurality of memory cell groups. Each scan flip flop includes a comparator for comparing the

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