Semiconductor integrated circuit device using BiCMOS technology

Details Semiconductor integrated circuit device using BiCMOS technology Semiconductor integrated circuit device using BiCMOS technology

2000-09-08

2001-11-06

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S156000, C365S230030, C365S177000

Reexamination Certificate

active

06314037

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a semiconductor integrated circuit device using BiCMOS technology.
2. Description of the Background Art
The BiMOS is a kind of circuit structure system in which a bipolar element and a MOS element are mixedly provided on the same chip, and is LSI technology in which a bipolar IC performing analog processes and an MOS IC performing digital processes with low consumption power are provided mixedly on the same chip.
The bipolar IC has an advantage that it can process high frequency signals and operate at high speed because it can perform analog processings with high accuracy and has large current driving capability. On the other hand, however, it has a disadvantage that the input impedance is low and consumption power is large. On the other hand, MOS IC has an advantage that the integrity level and input impedance are high but has a disadvantage that it is not suitable for analog processings.
Accordingly, a circuit configuration method, the BiMOS has been devised in order to realize semiconductor integrated circuit devices having advantages of both of bipolar IC and MOS IC. In order to make the most of strong points of both of the bipolar IC and the MOS IC, in a semiconductor integrated circuit device of BiMOS structure, a circuit portion for outputting TTL level signals includes a bipolar element and a MOS element, for example.
In the specification and drawings, N
1
-N
80
denote N-channel MOS field effect transistors (NMOS transistors), and P
1
-P
35
, P
61
-P
74
denote P-channel MOS field effect transistors (PMOS transistors). Also, B
1
-B
22
denote NPN-type bipolar transistors.
(1) Schematic Structure of the Entirety of Conventional SRAM (FIG.
45
)
FIG. 45
is a block diagram illustrating a schematic structure of a conventional general SRAM (Static Random Access Memory) using the BiMOS technology.
In a memory cell array
51
, a plurality of word lines and a plurality of bit line pairs are arranged intersecting one another and memory cells are provided at intersections thereof.
A row address buffer
52
applies row address signals X
0
-X
7
externally supplied to a row decoder
53
. Row decoder
53
selects one word line inside memory cell array
51
in response to a row address signal. A column address buffer
55
applies column address signals Y
0
-Y
6
provided from outside to a column decoder
56
. Column decoder
56
selects one bit line pair inside memory cell array
51
in response to a column address signal. Thus, a memory cell provided at an intersection of the selected word line and the selected bit line pair is selected. Data is written into the selected memory cell, or data stored in that memory cell is read out.
When both of a write enable signal {overscore (WE)} and a chip select signal {overscore (CS)} provided to a R/W control circuit
62
from outside attain “L”, data writing operation is performed. At this time, input data to be written is applied to an input pin DQ. The input data is applied to a write driver
61
through a data input/output buffer
59
and R/W control circuit
62
and written into a selected memory cell inside memory cell array
51
. When the writing operation is finished, bit line pairs inside memory cell array
51
are charged to a predetermined potential by a bit line load circuit
60
.
When a write enable {overscore (WE)} attains “H”, data reading operation is performed. Data stored in a selected memory cell inside memory cell array
51
is detected and amplified by a sense amplifier
58
and outputted to input/output pin DQ through data input/output buffer
59
.
The SRAM in
FIG. 45
has a common input and output pin. Also, redundant circuits such as a row redundancy circuit (row repair circuit)
54
and a column redundancy circuit (a column repair circuit)
57
are provided to enhance the yield.
(2) Detailed Structure of Respective Parts of Conventional SRAM
(a) Input Buffer Circuit (FIG.
46
)
FIG. 46
is a circuit diagram illustrating an input buffer circuit of TTL interface used in row address buffer
52
, column address buffer
55
and R/W control circuit
62
shown in FIG.
45
.
A power-supply potential Vcc is applied to a high potential side power-supply terminal (hereinafter, referred to as a power-supply terminal) and a ground potential GND is applied to a low potential side power-supply terminal (hereinafter, referred to as a ground terminal). In a semiconductor integrated circuit device of TTL interface, the power-supply potential Vcc is set to 5V and the ground potential GND is set to 0V.
In
FIG. 46
, a CMOS inverter
101
including transistors P
1
, P
2
, N
1
is connected between an input terminal I
1
and a node n
1
. A CMOS inverter
121
including transistors P
61
, N
61
and a CMOS inverter
123
including transistors P
63
, N
63
are connected between node n
1
and an output node
02
. A CMOS inverter
122
including transistors P
62
, N
62
, a CMOS inverter
124
including transistors P
64
, N
64
and a CMOS inverter
125
including transistors P
65
, N
65
are connected between node n
1
and an output node
01
.
In the case of TTL interface, an “H” level of an input signal A applied to input terminal I
1
is 2.2V and an “L” level is 0.8V. Accordingly, an amplitude of an input signal A is small and the “H” potential is low as compared to a CMOS level (“H”=5V, “L”=0V).
Therefore, it is adjusted so that a logical threshold value of the next stage is 1.5V by CMOS inverter
101
. 1.5V is an intermediate potential between 2.2V and 0.8V.
Specifically, a size of transistor N
1
is increased. Furthermore, the sizes of transistors N
61
and N
62
are increased so that logical threshold values of the next stages of CMOS inverters
121
and
122
become 2.5V which is intermediate potential between 5V and 0V.
CMOS inverters
123
,
124
,
125
work as driver circuits and have a decoder circuit connected to the next stage operate at a high speed.
As shown in
FIG. 46
, extra one stage of CMOS inverter
125
is required for obtaining complementary output signals B and {overscore (B)} in a CMOS circuit.
(b) WE Buffer Circuit (write enable buffer circuit) (FIGS.
47
and
48
)
FIG. 47
is a block diagram illustrating a WE buffer included in the R/W control circuit
62
shown in FIG.
45
and relating parts thereof.
FIG. 48
is a waveform diagram for use in describing operation of the WE buffer.
Referring to
FIGS. 47 and 48
, operation of the SRAM in
FIG. 45
will be described. Operation with the worst timing will be considered in which an address signal and an external write enable signal {overscore (WE)} change at the same timing (i.e., set up time=0 ns, and hold time=0 ns).
Period of Cycle CY
1
Since a write enable signal {overscore (WE)} attains “L” in the cycle CY
1
, the SRAM comes in a write state. In the write state, it is necessary that a fall of an internal write enable signal {overscore (IWE)} is later than switching of a word line.
This is because data is written into a memory cell selected with an address signal An−1 (erroneous writing) if an internal write enable signal {overscore (IWE)} falls before switching of word lines.
Period of Cycle Y
2
In cycle CY
2
, since a write enable signal {overscore (WE)} attains “H”, a SRAM comes in a read state. In the read state, it is necessary that a rise of an internal write enable signal {overscore (IWE)} is earlier than switching of word lines.
This is because it is possible that data is erroneously written into a memory cell selected with an address signal An+1 if an internal write enable signal {overscore (IWE)} rises before switching of a word line. This is also because a read time, that is, an access time becomes long since a time when potential of an “L” level of a bit line recovers to a potential close to power-supply potential Vcc in a read state is later than time of switching of word lines.
Accordingly, an internal write enable signal {overscore (IWE)} is required to respond sl

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