Semiconductor integrated circuit device, semiconductor...

Details Semiconductor integrated circuit device, semiconductor... Semiconductor integrated circuit device, semiconductor...

1999-06-23

2001-07-17

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S776000, C257S459000

Reexamination Certificate

active

06262487

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a multilayer wiring structure, a semiconductor integrated circuit wiring method, and a cell arranging method. More particularly, the present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit wiring technology, which are capable of achieving reduction in signal delay and improvement in noise resistibility in the semiconductor integrated circuit in which a wiring layer formed using oblique wiring grid is stacked on a wiring layer formed using X-Y wiring grid.
2. Related Art
As the multilayer wiring structure of a LSI according to the standard cell method or the gate array method in the prior art, there has been employed a method of stacking wiring layers, which are intersected orthogonally with each other, sequentially as an upper layer. In other words, the n-th layer is provided to intersect orthogonally with the (n−
1
)-th layer, e.g., the second layer is intersected orthogonally with the first layer, the third layer is intersected orthogonally with the second layer, so on. In such multilayer wiring structure in which respective layers are provided to intersect orthogonally with each other, if two points are to be connected along the diagonal direction of LSI, the points which are separated by a Euclidean distance must be connected. Therefore, a wiring which has a length in excess of a {square root over (
2
)} times distance of a linear distance is needed. Accordingly, in the orthogonal type multilayer wiring structure, overhead is caused in both an integration density and a delay characteristic.
However, an approach for designing wirings on the orthogonal coordinate system is convenient for an algorithm is LSI wiring design by using a computer. Therefore, the wirings have been designed by the computer without regard for the above overhead.
Meanwhile, with the progress of microfabrication of the circuit structure, an overall circuit performance is swayed by a delay component generated due to the wiring structure. Therefore, it has been impossible to disregard the above overhead caused when the wiring length is provided longer, as described above.
More particularly, first, a delay component due to the wiring resistance occupies the most part of the critical path delay. In this manner, an influence of the wiring length upon the circuit performance is now increasing.
Also, second, a coupling capacitance between neighboring wirings out of a load capacitance due to the wiring becomes dominant rather than a capacitance between the wiring and a substrate. As a result, in order to improve the circuit performance, it becomes an important factor how to reduce the capacitance between the neighboring wirings.
In addition, third, a malfunction which is caused by the coupling noise due to the coupling capacitance between the neighboring wirings becomes more serious. Particularly, in the wiring structure in the prior art in which all wirings are provided to intersect orthogonally with each other, if the neighboring wirings which are provided to extend in parallel in the same wiring layer are affected mutually, the upper and lower wirings are also extended in parallel even when the wiring is replaced with a wiring being placed in another wiring layer. For this reason, it is difficult to reduce the coupling capacitance between the wirings which are extended in parallel in the same wiring layer.
In connection with the orthogonal type multilayer wiring structure, there has been proposed an oblique wiring technology in which lengths of the wirings are reduced by using the oblique wirings (an oblique angle is 45° or 135°) in addition to the orthogonal wiring structure. For example, such oblique wiring technology has been disclosed in “An automatic layout method of a semiconductor integrated circuit” set forth in Patent Application Publication (KOKAI) Hei 5-102305. This prior art will be explained hereinbelow.
FIG. 1
is a view showing a layout of a wiring grid structure of a semiconductor integrated circuit device utilizing the oblique wirings in the prior art.
In this wiring grid structure, oblique wiring grids are formed as other layers on a layer which constitutes the orthogonal coordinates. In
FIG. 1
, a reference
401
denotes a wiring grid of a first layer. A wiring grid
402
of a second layer is formed on the first layer to orthogonally intersect with the first layer. In addition, a wiring grid
403
of a third layer is formed on the second layer
402
in the 45° oblique direction relative to the first layer
401
, and a wiring grid
404
of a fourth layer is formed on the third layer in the 135° oblique direction relative to the first layer
401
.
However, in the prior art, the multilayer wiring technology utilizing the oblique wirings has had problems as follows.
(1) In the multilayer wiring structure in the prior art, since the oblique wiring grid is provided simply, there has been a problem of a discrepancy between grid points. In other words, as shown in
FIG. 2
, a grid point formed by the first layer
401
and the second layer
402
is indicated by a reference
501
in FIG.
2
. While, a grid point formed by the third layer
403
and the fourth layer
404
is indicated by a reference
502
. In this case, if a contact hole (via hole) is formed from the fourth layer
404
to the third layer
403
, such hole is provided at the grid point
502
. On the other hand, if a via hole is formed from the third layer
403
to the second layer
402
, such hole is provided at the grid point
501
. However, if the grid point
501
is located in the close vicinity of the grid point
502
, no via hole can be provided, so that the via hole must be provided at another position. In this way, since discrepancy of the grid points is caused between the overlying oblique wiring lattices (the third layer
403
and the fourth layer
404
) and the underlying X-Y wiring lattices (the first layer
401
and the second layer
402
), the wiring design has become complicated.
(2) A resistance of the overlying oblique wiring layer becomes equal to the underlying wiring layer. Therefore, even if the oblique wiring layer is employed as the overlying layer. RC delay due to the wiring cannot be reduced. Where the term “RC delay” is delay which is generated by a resistance component R and a capacitance component C. For this reason, the wiring structure which is fitted for the global wiring to connect a long distance cannot be implemented by the overlying oblique wiring layer.
(3) Normally a wiring pitch of the overlying oblique wiring layers is not set wider than a minimum design rule. Therefore, the structure for reducing the neighboring wiring capacitance cannot be achieved by arranging the oblique wiring layer as the overlying layer. As for this respect, the second technology has been disclosed in Patent Application Publication (KOKAI) Hei 7-86414. According to the second technology, wirings located in the layer on which the most severe limitation of a wiring distance by the design rule is imposed are arranged obliquely with respect to the wiring grid on CAD. However, because this prior art cannot provide such a structure that a wiring width is not set wide simultaneously, the above wiring resistance cannot be reduced. In addition, because the coupling capacitance between the neighboring wirings is not reduced, RC delay of the wiring cannot be reduced.
(4) In the prior art, a profile of the via hole is defined as a rectangle. However, if the wirings other than the orthogonal wirings, i.e., the obliquely intersected wirings are connected mutually, it is impossible to assure a necessary and sufficient cut area by the rectangular via hole. Hence, sufficient resistibility for the electromigration phenomenon which brings about disconnection defect of the wiring has not been achieved.
(5) A relationship between the definition of a cell row which is formed by aligning logic cells in a row and the definition of an oblique wiring grid has not

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device, semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device, semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device, semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2445772