Semiconductor integrated circuit device, method of testing...

Details Semiconductor integrated circuit device, method of testing... Semiconductor integrated circuit device, method of testing...

2000-08-15

2003-09-23

Niebling, John F. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S030000, C714S726000, C714S729000

Reexamination Certificate

active

06625784

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit device including a scan test circuit, a method of testing the integrated circuit device, a database for use in design of the integrated circuit device and a method of designing the integrated circuit device.
An integrated circuit device, such as a system LSI, including a large number of circuits as well as a scan test circuit for testing these circuits is conventionally known.
FIG. 13
is a perspective view for illustrating a state of designing an integrated circuit device in which data of circuits to be designed are taken out from a data base. Data of the respective circuits are registered in the database as a core
1
, a core
2
, a core
3
and a core
4
, which are taken out from the database to be appropriately arranged in the integrated circuit device. As the data of these cores, data previously used may be reused or new data may be created.
Although not shown in
FIG. 13
, some integrated circuit devices include a scan test circuit for testing each logic circuit included therein. In a scan test method, flip-flops included in the integrated circuit device are used to test, for example, whether or not each element (a logic circuit, in particular) of the integrated circuit device is normally operated. These flip-flops are connected to one another, so as to form a scan test circuit working as a shift register in a test mode. An input/output pin of the integrated circuit device is used as a shift input/output terminal, so that the internal flip-flops can be accessed from the outside. In this method, an internal logic circuit can be dealt with as a combinational circuit, and thus, a self-diagnostic function can be realized. In this case, a combinational circuit means a circuit including merely an element not conducting a storage operation, such as an AND, an OR and a gate.
FIG.
14
(
a
) is a diagram for showing part of a conventional system LSI including a scan test circuit. As is shown in FIG.
14
(
a
), between a combinational circuit
110
and another combinational circuit
110
, that is, internal circuits of the system LSI, flip-flops
111
A through
111
F used for the scan test are disposed so as to be connected to each combinational circuit
110
. Although merely one combinational circuit
110
is shown in FIG.
14
(
a
), the system LSI actually includes a large number of combinational circuits, between which flip-flops for forming a scan test circuit are disposed.
Each flip-flop
111
has a terminal D for bringing in a data signal, a terminal DT for bringing in a scan test signal, a clock terminal for bringing in a clock signal, a terminal NT for bringing in a signal NT for setting an operation mode, and a terminal Q for outputting the scan test signal and the data signal. (Although not shown in the drawing, a general flip-flop additionally has a terminal/Q.)
The terminal Q of one flip-flop (for example,
111
A) is connected to the terminal DT of an adjacent flip-flop (for example,
111
B), so that a scan test circuit can be formed by serially connecting all the flip-flops
111
A through
111
F together. A scan-in signal input from an input pin, serving as a scan test signal input terminal, of the system LSI is received at the terminal DT of a flip-flop disposed at the top of one scan test circuit within the system LSI, and a scan-out signal is output from the terminal Q of a flip-flop at the last stage of the scan test circuit to the outside through an output pin of the system LSI. In general, on e system LSI includes several through dozens of scan test circuits.
In testing the system LSI, the input pin of the system LSI serving as the scan test signal input terminal and the output pin thereof serving as the scan test output terminal are connected to a tester, so as to receive the scan test signal DT output from the tester at the scan test signal input terminal and to send the data signal D having passed through the combinational circuit of the system LSI (namely, a data value obtained from the scan test signal having passed through the combinational circuit) to the tester. The tester compares the value of the data signal D with an expected value, thereby determining whether or not each element of the combinational circuit
110
is defective.
In this test of the system LSI using the tester, the signal NT is switched to enter the test mode. In particular, the test mode for the scan test is classified into a shift mode and a capture mode.
FIG.
14
(
b
) is a diagram for showing change with time of control during the scan test. While the signal NT is in the shift mode, the scan test signal DT is supplied to the flip-flops
111
A through
111
F. In other words, the scan test signal is successively sent from the terminal Q of one flip-flop to the terminal DT of another flip-flop at the next stage every clock, so that all the flip-flops constituting the scan test circuit can hold the scan test signal to be input to the combinational circuit. This takes time corresponding to the number of clocks (which is several hundred clocks or more in general) equal to the number of flip-flops included in the scan test circuit (namely, time corresponding to several hundred clock periods or more). With the scan test signal DT held by the flip-flops
111
A through
111
F, the signal NT is switched to enter the capture mode, so that each of the flip-flops
111
A through
111
F can fetch the data signal. In this case, the flip-flops
111
A through
111
F simultaneously fetch the data signal, and hence, the capture operation takes time corresponding to one clock. The data signal D is a signal having passed through the combinational circuit
110
, and has an output value corresponding to the value of the scan test signal DT having been input to the combinational circuit
110
. Then, in a subsequent test mode, a next scan test signal DT is sent to the flip-flops
111
A through
111
F, and at the same time, the data signals D held by the flip-flops
111
A through
111
F are sent from the output pin to the tester. When the shift operation is completed, each of the flip-flops
111
A through
111
F included in the scan test circuit holds the scan test signal DT instead of the data signal D fetched in the capture mode. Thereafter, the capture mode and the shift mode are alternately repeated.
In this manner, by comparing an expected value, which is expected to be obtained by allowing the scan test signal DT input to the combinational circuit
110
to pass through the combinational circuit, with the data signal D actually output from the combinational circuit
110
, it can be determined whether or not the combinational circuit
110
is defective.
In conducting the scan test, it is necessary to simultaneously operate as many combinational circuits as possible so as to complete the scan test of the integrated circuit device in a short period of time. This is because, when the tester is used for a long period of time, the cost of the integrated circuit device ultimately becomes high due to high running cost of the tester.
Therefore, in general, in sending a scan test signal to the flip-flops, test patterns in accordance with the number of flip-flops are respectively shifted by the number of clocks equal to the number of the flip-flops, and then the capture operation is started after one clock.
When a large number of cores are operated in a short period of time as in the aforementioned scan test of the integrated circuit device, however, the momentary power consumption (peak power consumption) during the test can be very large. Particularly, since a large number of and a variety of circuits are recently packed in one chip of an integrated circuit device such as a system LSI, the peak power consumption is estimated to be extremely large.
FIG. 15
is a diagram for exemplifying change with time of power consumption in the entire integrated circuit device during the scan test. As is shown in
FIG. 15
, the power consumption during the test is momentarily increased by operating the cores
1
through
4
simultaneously (namely,

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device, method of testing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device, method of testing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device, method of testing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3048515