Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-29
2008-07-29
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S194000, C365S225700, C365S201000, C714S741000, C714S037000
Reexamination Certificate
active
07406643
ABSTRACT:
A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, an output register, a register controlled by a register control a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.
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Honmura Tetsuro
Ishibashi Koichiro
Osada Kenichi
Yano Kazuo
Britt Cynthia
Kenyon & Kenyon LLP
Renesas Technology Corporation
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