Semiconductor integrated circuit device having circuit inspectio

Details Semiconductor integrated circuit device having circuit inspectio Semiconductor integrated circuit device having circuit inspectio

1993-07-23

1994-09-27

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, 365201, 365233, G11C 700, G11C 2900

Patent

active

053512111

ABSTRACT:
An integrated circuit including latch circuits disposed on the input and output sides of an object circuit the delay time of which is to be measured, respectively, and a variable delay circuit capable of arbitrarily delaying a timing signal supplied from outside or a timing signal generated inside the integrated circuit by an instruction from outside. The timing signal and a delay signal obtained by delaying the input signal by the variable delay circuit are supplied as clock signals to the latch circuits, and the signal passing through the variable delay circuit is fed back to the input side so as to constitute an oscillation circuit, the oscillation signal of which can be outputted to outside. A signal delayed by a desired time can be automatically generated inside the semiconductor integrated circuit on the basis of this timing signal.

REFERENCES:
patent: 4128900 (1978-12-01), Lappington
patent: 4392105 (1983-07-01), McLeod
patent: 4489272 (1984-12-01), McLeod
patent: 4575824 (1986-03-01), Tanaka et al.
patent: 4608669 (1986-08-01), Klara et al.
patent: 4849973 (1989-07-01), Kubota
patent: 4962500 (1990-10-01), Nakagawa
patent: 5077690 (1991-12-01), Smith
patent: 5291449 (1994-03-01), Dehara

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