Semiconductor integrated circuit device having back-bias voltage

Details Semiconductor integrated circuit device having back-bias voltage Semiconductor integrated circuit device having back-bias voltage

1985-08-08

1988-10-04

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 700, G11C 1140

Patent

active

047759593

ABSTRACT:
In typical MOS integrated circuit devices, the level of the back-bias voltage which is generated by a built-in back-bias generation circuit and is supplied to a semiconductor substrate is changed by an undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant. Instead, it becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, a back-bias voltage generation circuit is provided which has output capacity of a plurality of levels. Its output capacity is increased in response to an operation control signal of the main circuit. The level change of the back-bias voltage generation circuit can further be reduced by providing a level detection circuit for detecting the level change and a feedback circuit for controlling the back-bias voltage generation circuit in accordance with the output of the level detection circuit.

REFERENCES:
patent: 4161791 (1979-07-01), Leach
patent: 4263664 (1981-04-01), Owen et al.
patent: 4393481 (1983-07-01), Owen et al.
patent: 4492973 (1985-01-01), Ogura
patent: 4581718 (1986-04-01), Oishi
"Nikkei Electronics" May 14, 1979, pp. 77-79.

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