Semiconductor integrated circuit device having a test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S743000

Reexamination Certificate

active

06964000

ABSTRACT:
32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits are input to 10 flip-flops serially arranged in an address shift register for each clock cycle, a read address expressed by a string of bits output from the flip-flops of odd-numbered stages is input to a read port of a RAM to perform a read test for one memory cell of the read address, and a write address expressed by a string of bits output from the flip-flops of even-numbered stages is input to a write port of the RAM to perform a write test for one memory cell of the write address. The read test and the write test for 32 memory cells are alternately performed in 64 clock cycles.

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J. Otterstedt, et al., “Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests”, IEEE, International Test Conference 1998 Proceedings, Paper 3.1, Oct. 18-23, 1998, pp. 53-62.

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