Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-11-04
1999-06-08
Ganney, Vincent P.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
G06F 1100
Patent
active
059101814
ABSTRACT:
A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector, and are provided to the core unit of the synchronous dynamic random access memory for testing.
REFERENCES:
patent: 5629898 (1997-05-01), Idei et al.
patent: 5761149 (1998-06-01), Suzuki et al.
Hatakenaka Makoto
Tomishima Shigeki
Yamagata Tadato
Yamazaki Akira
Ganney Vincent P.
Mitsubishi Denki & Kabushiki Kaisha
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