Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-03-08
2005-03-08
Tran, Andrew Q. (Department: 2824)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S731000, C365S201000, C365S233100, C365S196000, C365S202000, C365S189050, C365S220000
Reexamination Certificate
active
06865705
ABSTRACT:
A semiconductor integrated circuit device comprises a control unit for switching a mode about the trimming or estimation in an internal circuit, the control unit including a controller capable of realizing the mode switching control about the trimming or estimation by the JTAG method. The controller includes an instruction decoder for decoding an input instruction, a shift scan register circuit for enabling a boundary scan based on the decoded result of the instruction decoder, and an operation controller for controlling the operations of the instruction decoder and the shift scan register circuit. Therefore, the trimming becomes possible after sealing a semiconductor chip into a package.
REFERENCES:
patent: 5970005 (1999-10-01), Yin et al.
patent: 6163499 (2000-12-01), Suzuki
patent: 6473352 (2002-10-01), Nishino et al.
patent: 11-31398 (1999-02-01), None
patent: 11-289322 (1999-10-01), None
Nishiyama Masahiko
Tomizawa Masahiko
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Hitachi Ulsi Systems Co., Ltd.
Reed Smith LLP
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