Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-04-22
1999-11-16
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
059876352
ABSTRACT:
An image processor, included in a logic circuit unit, for executing an image processing of data according to the MPEG standard and the like, a memory circuit unit, whose input port is included in the logic circuit unit, for storing image processed data, and a memory control unit, included in the logic circuit unit, for controlling the input/output operation of the memory circuit unit are formed on a semiconductor substrate. Between the memory circuit unit and the memory control unit, a selector is interposed for selecting, in accordance with a test mode signal, an externally input first chip select control signal when the test mode signal is activated, and selecting a second chip select control signal output by a memory control circuit and outputting a chip select signal to the memory circuit unit when the test mode signal is deactivated.
REFERENCES:
patent: 4709279 (1987-11-01), Sano et al.
patent: 5111433 (1992-05-01), Miyamoto
patent: 5369611 (1994-11-01), Miura
patent: 5604756 (1997-02-01), Kawata
Kishi Tetsuji
Nagasaki Yoshimichi
Matsushita Electric - Industrial Co., Ltd.
Nguyen Hoa T.
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