Semiconductor integrated circuit device capable of...

Details Semiconductor integrated circuit device capable of... Semiconductor integrated circuit device capable of...

2001-03-19

2002-06-04

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189020, C365S189050, C365S230080

Reexamination Certificate

active

06400625

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices and particularly to a system LSI equipped with a memory. More particularly, the present invention relates to a configuration of a test interface circuit for externally and directly testing a memory in the system LSI.
2. Description of the Background Art
A system LSI such as a logic merged DRAM has been developed in which a logic such as a processor and an ASIC (Application Specific Integrated Circuit) and a dynamic random access memory (DRAM) of mass storage capacity are integrated on one semiconductor chip (semiconductor substrate). In such a system LSI, interconnection of a logic and a memory such as a DRAM by a multi-bit internal data bus of 128 to 512 bits can attain a data transfer rate higher than that of a general purpose DRAM by at least one or two orders of magnitude.
Since the DRAM and the logic are connected by an internal interconnection, the length of the internal interconnection is sufficiently shorter and has smaller parasitic impedance than an on-board interconnection. That results in achievement of substantial reduction in the charging/discharging current of a data bus as well as signal transmission at high speed. In addition, the number of external pin terminals in the logic can be reduced as compared with a type in which a general purpose DRAM is externally provided for the logic.
From these reasons, the system LSI such as a logic merged DRAM greatly contributes to attaining higher performance of information devices which carry out processing dealing with mass data such as three dimensional graphics processing and image/audio processing.
In the above described system LSI such as a logic merged DRAM, only the logic is coupled to the external pin terminals via a pad. Therefore, when the function of a memory such as a contained DRAM is to be tested, the test needs to be performed through the logic. In this case, however, the logic performs a control operation for testing, which increases the load of the logic. In addition, it becomes necessary to externally supply the logic with an instruction to perform a functional test for a memory such as a DRAM, to give from the logic to the memory a control signal for performing the functional test, and to read out the test result through the logic.
Therefore, the memory functional test in the system LSI such as a logic mixed DRAM is carried out through the logic, and the operating timing margin for the memory and the like cannot be tested correctly.
In view of program capacity as well, the number of test patterns provided by the logic is limited, and sufficient testing cannot be performed. Because of the factors, it is difficult to sufficiently ensure the reliability of a memory such as a DRAM. Since the probability of defect generation in the logic itself becomes higher with increase in the gate scale, the reliability of memory testing is lowered. Therefore, it becomes necessary to directly test a memory such as a DRAM from outside by using a dedicated tester including a memory tester. Hereinafter, the system LSI with contained DRAM is referred to as a DRAM contained system LSI.
FIG. 26
schematically shows a configuration of a conventional DRAM contained system LSI
900
.
Referring to
FIG. 26
, system LSI
900
includes a large scale logic LG coupled to external pin terminals LPGA and performing directed processing, an analog core ACR coupled between large scale logic LG and external pin terminals APG and performing processing for an analog signal, a DRAM core MCR coupled to large scale logic LG through an internal interconnection and storing data required by large scale logic LG, and a test interface circuit TIC disconnecting large scale logic LG and DRAM core MCR in a test mode and coupling an external memory tester to DRAM core MCR through test pin terminals TPG. DRAM core MCR receives a power supply voltage VCC through a power supply terminal PST.
Analog core ACR includes a phase locked loop circuit (PLL) generating an internal clock signal, an analog/digital converter converting an external analog signal to a digital signal, and a digital/analog converter converting a digital signal applied from large scale logic LG to an analog signal and outputting the analog signal.
DRAM core MCR which is a synchronous DRAM (SDRAM) captures data and an operation mode designation signal and outputs data in synchronization with an applied clock signal.
Large scale logic LG includes a memory control unit for carrying out processing such as image/audio information processing and controlling access to DRAM core MCR.
As shown in
FIG. 26
, provision of test interface circuit TIC makes it possible to completely disconnect DRAM core MCR from the logic portion (large scale logic LG) so as to directly access DRAM core MCR through test pin terminals TPG and to directly and externally control and observe DRAM core MCR. Such a test procedure is called direct memory access testing. By providing test interface circuit TIC, an operational test of a similar level to that for a general purpose DRAM (SDRAM) using a conventional memory tester can be performed.
FIG. 27
shows a configuration of test interface circuit TIC shown in FIG.
26
and associated portions.
Referring to
FIG. 27
, test pin terminals TPG include a pin terminal receiving a test clock signal TCLK
1
, a pin terminal receiving a test control signal TCMD for designating a test operation mode, a pin terminal receiving a test address TAD for designating a memory cell in DRAM core MCR which is to be accessed in a test mode, a pin terminal receiving write data TDin in the test mode, and a pin terminal receiving output data TDout from test interface circuit TIC in the test mode.
Test write data TDin applied to test interface circuit TIC and test output data TDout from test interface circuit TIC are set to the bit width of 8 bits, for example, similarly to a general purpose DRAM.
Test interface circuit TIC includes a latch/command decoder
1
capturing, in synchronization with test clock signal TCLK
1
, test control signal TCMD, test address TAD and test write data TDin applied to test pin terminals TPG, and performing processing such as decoding the test control signal to an internal command (operation mode designation signal) to be issued to DRAM core MCR and expanding test input data TDin of a 8-bit width to write data of 256 bits, a mode register
2
storing information such as the column latency of DRAM core MCR, a CA shifter
3
shifting, according to the column latency information stored in mode register
2
, a read selection designation signal applied from latch/command decoder
1
to produce a read data selection signal RD_S, and a 256:8 selection circuit
4
selecting, according to read data selection signal RD_S from CA shifter
3
, 8-bit data from the 256-bit read data read out from DRAM core MCR. Hereinafter, the 256:8 selection circuit is also referred to as a read data selection circuit.
As test peripheral circuits, a selector
5
selectively coupling DRAM core MCR and one of the large scale logic LG and test interface circuit TIC in response to test mode designation signal TE, a gate circuit
6
receiving clock signal CLK applied from the large scale logic LG, for example, in a normal operation mode and test clock signal TCLK
1
applied in the test mode and supplying a clock signal DCLK to DRAM core MCR, and a gate circuit
7
transmitting to test interface circuit TIC 256-bit read data RD read out from DRAM core MCR at the time of activation of test mode designation signal TE are provided. 256-bit read data RD read out from DRAM core MCR is applied to the large scale logic LG without passing through selector
5
. This is intended to apply read data at high speed to the large scale logic in the normal operation.
DRAM core MCR captures applied data and signals and outputs read data RD in synchronization with DRAM operational clock signal DCLK.
FIG. 28
shows in more detail the configuration of latch/command decoder
1
shown in FIG.
27
.
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