Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-07
2006-11-07
Quach, T. N. (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S655000, C438S682000
Reexamination Certificate
active
07132341
ABSTRACT:
In a high-performance semiconductor integrated circuit, the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM. A gate electrode G is formed on semiconductor substrate1and n+-type semiconductor regions17(source/drain regions) are formed in the semiconductor substrate on both sides of this gate electrode. Within the same apparatus and under near-vacuum conditions, a depth of 2.5 nm or less is etched away from the surfaces of the source/drain regions and gate electrode, a film of Co is then formed on the source/drain regions, and thermal processing is applied to form CoSi2layer19a. As a result, current leakage in the memory cell can be prevented and this method can be applied to semiconductor integrated circuit devices that have low current consumption or are battery-driven.
REFERENCES:
patent: 5344793 (1994-09-01), Zeininger et al.
patent: 5780929 (1998-07-01), Zeininger et al.
patent: 6096638 (2000-08-01), Matsubara
patent: 6117723 (2000-09-01), Huang
patent: 6239006 (2001-05-01), Shields
patent: 6303503 (2001-10-01), Kamal et al.
patent: 0 325 328 (1989-07-01), None
patent: 7-161660 (1995-06-01), None
patent: 9-320987 (1997-12-01), None
Wolf, S., Silicon Processing for the VLSI Era, vol. 2, Lattice Press, 1990, pp. 150-152.
Hong, Q., et al., CoSi2 with Low Diode Leakage . . . , IEDM Tech. Digest, Dec. 1997, pp. 107-110.
Rho, K., et al., Dependence of Deep Submicron CMOSFET Characteristics . . . , International Conference of Microelectronics and VLSI, Nov. 1995, pp. 291-294.
Yan, R., et al., High Performance 0.1 um Room Temperature Si MOSFETs, Symposium on VLSI Digest of Technical Papers, 1995, pp. 86-87.
Lee, S., et al., A High Performance 0.13 um CMOS Process . . . , IEEE 6th International Conference of VLSI and CAD, Oct. 1999, pp. 136-139.
Endo Fumiaki
Kanazawa Hideaki
Kojima Masanori
Sahara Masashi
Sugiura Masakazu
Hitachi ULSI Systems Co. Ltd.
Quach T. N.
Renesas Technology Corp.
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