Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-21
2006-11-21
Torres, Joseph D. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S732000
Reexamination Certificate
active
07139956
ABSTRACT:
A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.
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Yasuyuki Nozuyama, “Semiconductor Integrated Circuit Including A Test Facilitation Circuit For Functional Blocks Intellectual Properties And Automatic Insertion Method Of The Same Test Facilitation Circuit ” Ser. No. 09/960,414, filed Sep. 24, 2001.
Notification of Reasons for Rejection issued by Japanese Patent Office mailed Apr. 25, 2006, in Japanese Application No. 2001-063725 and English translation of Notice.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Torres Joseph D.
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