Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-02-11
2001-05-01
Elms, Richard (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S227000, C365S229000, C365S185180, C365S189070
Reexamination Certificate
active
06226224
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device and a storage device. More specifically, the invention relates to the semiconductor integrated circuit device and the storage device for raising a power supply voltage supplied from the outside to drive a semiconductor circuit, such as a flash memory, which is capable of batch erasing stored data.
2. Description of the Background Art
A flash memory, which is a kind of a non-volatile semiconductor memory, comprises a matrix arrangement of electrically erasable programmable read-only memory (EEPROM) cells, which are capable of electrically writing and erasing data.
FIG. 25
is a diagram illustrating the structure of a non-volatile semiconductor memory of this type. Each of memory cells in a semiconductor chip comprises a stack gate type transistor having a floating gate FG and a control gate CG. When electrons are injected into the floating gate FG or when electrons are emitted from the floating gate FG, a threshold voltage varies. By utilizing this variation in threshold voltage, data are written in and read out of the respective memory cells.
Specifically, logic “1” or “0” is determined by whether or not the current flows when the power supply voltage is applied to the control gate CG of a memory cell to be read out. The threshold voltage of a memory cell is about 2 V when the memory cell has logic “1” and higher than or equal to 5 V when it has logic “0”.
In a conventional flash memory, since both of a power supply voltage supplied from the outside and a control gate voltage during readout are set to 5 V, there is particularly no problem even if the power supply voltage is applied directly to a control gate CG during readout.
In recent years, with the miniaturization of memory cells and the increase of memory capacity, it is required to lower the power supply voltage supplied from the outside; therefore, the external power supply voltage has generally been set to 3 V.
When the power supply voltage is set to 5 V as the prior art, the difference between the voltage VG applied to the control gate CG during readout and the threshold voltage Vth when the memory cell has logic “1” is VG−Vth=5−2=3 V. On the other hand, when the power supply voltage is 3 V, VG−Vth=3−2=1 V, which is a third of that when the power supply voltage is 5 V, so that the current flowing through the memory cell (which will be hereinafter referred to as a “cell current”) is decreased. The decrease of the cell current decreases the readout rate, and also decreases the margin of fluctuation in the power supply voltage.
Consequently, there is proposed a technique for raising the power supply voltage, which is supplied from the outside (which will be hereinafter referred to as an “external power supply voltage Vccext”) in a semiconductor chip, to higher voltage than 3 V, to generate an internal voltage Vccint, and for applying the internal voltage Vccint to the control gate of the memory cell. This internal voltage Vccint must be set to 5 V even in a stand-by state, in which data are not written in and read out of the memory cell. Because if the internal voltage Vccint is set to be lower than 5 V during the stand-by state, the voltage level of the internal voltage Vccint must be started to rise immediately after the operation state is switched from the stand-by state to a memory access state. Therefore, it takes a lot of time until the internal voltage Vccint reaches 5 V, so that it is not possible to read data out of the memory cell during that period of time.
Accordingly, the voltage level of the internal voltage Vccint in the stand-by state must be set to the same as that in the memory access state. In addition, since a non-volatile memory, such as a flash memory, is often used for a portable apparatus driven by a electric battery, the power consumption during the stand-by state is preferably as low as possible.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to eliminate the aforementioned problems and to provide a semiconductor integrated circuit device, which can supply a higher voltage than a voltage supplied from the outside to a semiconductor circuit and a storage device, such as a flash memory, with a low power consumption and which can prevent the voltage supplied to the semiconductor circuit and the storage device from fluctuating even if the operation state is switched.
To achieve the above-mentioned object, the present invention provides a semiconductor integrated circuit device comprising:
a booster circuit for raising a voltage supplied from an outside;
a semiconductor circuit driven by a voltage depending on a stepped-up voltage raised by said booster circuit;
a first level detecting circuit for detecting fluctuation in said stepped-up voltage during a first operation state of said semiconductor circuit; and
a second level detecting circuit for detecting fluctuation in said stepped-up voltage during a second operation state of said semiconductor circuit, said second level detecting circuit being formed by a circuit having a lower power consumption than that of said first level detecting circuit.
The present invention provides a semiconductor integrated circuit device comprising:
a booster circuit for raising a voltage supplied from an outside;
a semiconductor circuit driven by a voltage depending on a stepped-up voltage raised by said booster circuit; and
an internal voltage generating circuit for generating an internal voltage on the basis of said stepped-up voltage, said internal voltage generating circuit setting said internal voltage to a lower voltage level than said stepped-up voltage during a first operation state of said semiconductor circuit, and setting said internal voltage to a voltage level substantially equal to said stepped-up voltage during a second operation state of said semiconductor circuit.
The present invention provides a semiconductor integrated circuit device comprising:
a booster circuit for raising a voltage supplied from an outside;
a semiconductor circuit driven by a voltage depending on a stepped-up voltage raised by said booster circuit; and
a level detecting circuit for detecting fluctuation in said stepped-up voltage,
wherein said booster circuit comprises a pulse generator for generating a pulse signal, and a charging pump for raising said voltage in accordance with said pulse signal, a level detecting operation of said level detecting circuit being controlled by said pulse signal.
The present invention provides a semiconductor integrated circuit device comprising:
a booster circuit for raising a voltage supplied from an outside;
a semiconductor circuit driven by a voltage depending on a stepped-up voltage raised by said booster circuit,
a level detecting circuit for detecting fluctuation in said stepped-up voltage;
a reference voltage generating circuit for generating a reference voltage of a predetermined voltage level on the basis of said voltage supplied from the outside; and
wherein a current consumption of said level detecting circuit and said reference voltage generating circuit are controlled by a common constant current source.
The present invention provides a semiconductor integrated circuit device comprising:
a booster circuit for raising a voltage supplied from an outside;
a semiconductor circuit driven by a voltage depending on a stepped-up voltage raised by said booster circuit; and
an internal voltage generating circuit for generating an internal voltage on the basis of said stepped-up voltage, said internal voltage generating circuit comprising:
a switching circuit for switching whether output terminals of said booster circuit and said internal voltage generating circuit are short-circuited or not; and
a switch control circuit for controlling said switching circuit so that said internal voltage becomes substantially equal to said stepped-up voltage, when said internal voltage becomes lower than or equal to a predetermined voltage after
Atsumi Shigeru
Banba Hironori
Shiga Hitoshi
Umezawa Akira
Banner & Witcoff , Ltd.
Elms Richard
Kabushiki Kaisha Toshiba
Nguyen Vanthu
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