Semiconductor integrated circuit device and process for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S257000, C438S262000, C438S593000

Reexamination Certificate

active

07105409

ABSTRACT:
A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions205formed first conduction type well201, floating gates203bformed on semiconductor substrate200through an insulator film202, control gates211aformed on floating gates203bthrough nitrogen-introduced silicon oxide film210aand third gates207adifferent from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates207athus formed is made lower than that of floating gates203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

REFERENCES:
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 5541130 (1996-07-01), Ogura et al.
patent: 5555520 (1996-09-01), Sudo et al.
patent: 5614747 (1997-03-01), Ahn et al.
patent: 5654917 (1997-08-01), Ogura et al.
patent: 5672892 (1997-09-01), Ogura et al.
patent: 5681770 (1997-10-01), Ogura et al.
patent: 5682055 (1997-10-01), Huang et al.
patent: 5780341 (1998-07-01), Ogura
patent: 6034894 (2000-03-01), Maruyama et al.
patent: 6150691 (2000-11-01), Clampitt
patent: 6326293 (2001-12-01), Fang et al.
patent: 6438028 (2002-08-01), Kobayashi et al.
patent: 6687156 (2004-02-01), Kobayashi et al.
patent: 6797566 (2004-09-01), Kobayashi et al.
patent: 63-25979 (1988-02-01), None
patent: 7-130884 (1995-05-01), None
patent: 07-130884 (1995-05-01), None
patent: 8-340095 (1996-12-01), None
patent: 9-116119 (1997-05-01), None
patent: 9-321157 (1997-12-01), None
patent: 11-220044 (1999-08-01), None
Kume, Hitoshi, “Flash Memory Technology,” Ohyobutsuri, 65, No. 11, pp. 1114-1124, Nov. 10, 1996 (Japan Society of Applied Physics).
Naruke, K. et al., “A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side”, IEEE Technical Digest of International Electron Devices Meeting, 1989, pp. 603-606.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor integrated circuit device and process for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device and process for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and process for... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3555982

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.