Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-10
2004-05-11
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S241000, C438S243000, C438S253000
Reexamination Certificate
active
06734060
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technique and, more particularly, to a technique which is effective when applied to the process for manufacturing a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory) and a semiconductor integrated circuit device technique.
The DRAM has a memory cell comprising one memory cell selecting MIS transistor and a capacitor connected in series with the MIS transistor so that its degree of integration is high enough to lower the unit price per bit. Therefore, DRAMs are widely used in main memories for various computers or communication devices that require a memory of high storage capacity.
The memory capacity of the DRAM has a tendency to increase more and more. In accordance with this tendency, the area occupied by the memory cell tends to decrease with a view to improving the degree of integration of the memory cells of the DRAM.
However, the capacitance of the information storage capacitive element (capacitor) in a memory cell of a DRAM is required to be a certain value from the standpoint of considering the operation margin, soft errors and so on, independently of the DRAM generation, and cannot be proportionally reduced, as generally known in the art.
Thus, the capacitor structure has been developed to have a necessary capacitance in a limited small occupation area. In one of the results of these developments a three-dimensional capacitor structure such as the so-called “stacked capacitor”, in which two layers of capacitor electrodes are stacked through a capacitor insulation film is adopted.
The stacked capacitor generally has a structure in which the capacitor electrodes are arranged over a memory cell selecting MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and represented by a cylindrical or fin type capacitor structure. Either of these is characterized in that a large capacitance can be ensured by increasing the size in the height direction of the capacitor but without increasing the size in the widthwise direction of the capacitor.
A DRAM having memory cells is disclosed in Japanese Patent Laid-Open No. 122654/1995 relating to the so-called “Capacitor Over Bitline (will be abbreviated to COB)” in which the information storage capacitive elements are provided in a layer over bit lines.
SUMMARY OF THE INVENTION
We have found out the following problems in the above-specified technique.
Specifically, the connection hole for electrically connecting different wiring layers or a wiring line and a semiconductor substrate has a such a high aspect ratio as to make it difficult to open a connection hole and to fill it in with a conductor layer. This problem is serious in the case of the connection hole portion for connecting the upper wiring layer and the lower wiring layer in the stacked capacitor especially when the information storage capacitive element of the DRAM is a stacked capacitor. This is caused by the deepened connection hole because the capacitance of the capacitor is increased without increasing the occupation area.
We have studied the prior art from the view point of the wiring structure of the DRAM and have found PCT Laid-Open No. 9719468, for example, on that technique. This Laid-Open discloses the structure in which three buried wiring layers are interposed between the capacitor and the semiconductor substrate of the DRAM. Also disclosed is a structure in which multiple plugs are stacked, but there is no mention of the structure in which the lines buried in the layer common to the bit lines are led out through the stacked plugs to the wiring layer over the capacitor.
An object of the invention is to provide a technique capable of facilitating the works to open a connection hole for connecting different wiring layers and to fill in the connection hole with a conductor film.
The above-specified and other objects and the novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representative aspects of the invention to be disclosed herein will be briefly described in the following.
According to the invention, there is provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising forming a bit line and a first line in the same wiring layer over the semiconductor substrate; forming the information storage capacitive element over the bit line not through another wiring layer line; and forming a second line over the information storage capacitive element, wherein the process further comprises forming between the first line and the second line a first connection portion electrically connected in direct contact with the first line, and a second connection portion electrically connected in direct contact with the first connection portion.
In a semiconductor integrated circuit device manufacturing process according to the invention, moreover, the second connection portion has a planar size larger than that of the first connection portion.
In a semiconductor integrated circuit device manufacturing process of the invention, moreover, the second connection portion has a planar size larger than that of the first connection portion to an extent that it includes a plurality of the first connection portions.
According to the invention, there is further provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising:
(a) forming a bit line and a first line in the same wiring layer over said semiconductor substrate;
(b) forming over said semiconductor substrate a first insulation film covering the bit line and the first line;
(c) opening in the first insulation film a first connection hole for exposing the first line in the region other than the region where the memory cell is formed;
(d) forming the first connection portion by filling it in with a first conductor film;
(e) forming a second insulation film made of a material allowing a relatively high etching selection ratio for the first insulation film in such a way as to cover the upper faces of the first insulation film and the first connection portion;
(f) forming the information storage capacitive element over the bit line in said memory cell forming region;
(g) opening a second connection hole for exposing the first connection portion in the region other than the region where the memory cell is formed in the second insulation film formed between the wiring layer over the information storage capacitive element and the first connection portion, and in a third insulation film made of such a material to allow a relatively high etching selection ratio for the second insulation film; and
(h) forming a second connection portion electrically connected in direct contact with the first connection portion, by burying a second conductor film in the second connection hole.
According to the invention, moreover, there is further provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising:
(a) forming a bit line and a first line in the same wiring layer over the semiconductor substrate;
(b) forming over the semiconductor substrate a first insulation film covering the bit line and the first line;
(c) opening in the first insulation film a first connection hole for exposing the first line in the region oth
Asano Isamu
Kawakita Keizou
Nakamura Yoshitaka
Yamada Satoru
Antonelli Terry Stout & Kraus LLP
Chaudhuri Olik
Hitachi , Ltd.
Maldonado Julio J.
LandOfFree
Semiconductor integrated circuit device and process for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and process for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and process for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3246334