Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-03-08
2008-12-02
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S081000
Reexamination Certificate
active
07459929
ABSTRACT:
The present invention discloses a semiconductor integrated circuit device and an on-die termination circuit. The circuit includes a level shifter for boosting an on-die termination control signal to a high voltage level; and a first NMOS transistor connected between a power voltage and a pad and terminating the pad to a first termination voltage level in response to the high voltage level. The on-die termination circuit has a reduced input capacitance.
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English language abstract of Japanese Publication No. 09-018326.
English language abstract of Korean Publication No. 2003-0083237.
Cho James H.
Crawford Jason
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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