Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-17
2004-03-16
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S217000, C438S232000, C438S291000, C438S301000, C438S305000, C438S525000, C438S527000, C438S656000, C438S659000, C438S683000
Reexamination Certificate
active
06706582
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, the invention relates to the manufacture of MISFET (metal insulator semiconductor field effect transistor) having a so-called punch through stopper structure and also to a technique effective for application to the MISFET.
For the purpose of improving the drive ability of MISFET, the reduction in gate length of MISFET is now in progress. A shorter gate length of MISFET results in a shorter channel length, rendering the distance between a source and a drain shorter. This affords great influences of the source and drain characteristics on the electric field and potential distribution. One of the influences includes a short channel effect wherein when a channel length is at a certain level or below, the threshold voltage of MISFET abruptly lowers.
One of the phenomena caused by the short channel effect includes a lowering of the breakdown voltage between the source and drain of the MISFET. This is ascribed to a so-called punch through wherein a shorter gate length leads to the connection between a source depletion layer and a drain depletion layer, under which an electric current passes across the source and drain although any channel between the source and drain is not formed.
The punch through is divided into two categories including a shallow punch through that occurs in the vicinity of the surface of a semiconductor substrate and a deep punch through that occurs at a depth of about 0.1 &mgr;m or over from the surface of the semiconductor substrate. In order to suppress the occurrence of such punch throughs, a technique of providing a so-called punch through stopper (PTS) is known. The PTS structure includes a case wherein an impurity ion of a conduction type opposite to that of source-drain is ion implanted once thereby forming a pocket structure in the vicinity of a source-drain or LDD (lightly doped drain) structure, and another case wherein a similar impurity ion is implanted into the whole area of a channel region, thereby forming a PST structure wholly over the area.
The technique of suppressing the punch through by formation of the PTS structure is described, for example, in Japanese Laid-open Patent Application No. 2000-196079.
SUMMARY OF THE INVENTION
We have found that the above-stated PTS structures have the following problems.
With the whole-area PTS structure, in order to suppress a punch through in case where the gate electrode of MISFET becomes fine, it becomes necessary to increase an impurity concentration in a semiconductor substrate in which MISFET is to be formed. To this end, the threshold voltage of MISFET cannot be lowered, with the attendant problem that the drive ability of MISFET cannot be improved.
On the other hand, with the case of the pocket structure formed by vertically implanting an impurity ion, when a shallow punch through is suppressed by the action of the pocket structure, an impurity concentration at the deep region of the channel becomes higher than as desired. This results in an increasing junction capacitance and junction leakage current, with the problem that the drive ability of MISFET cannot be improved.
With the pocket structure formed by implanting an impurity ion obliquely, when a deep punch through is suppressed by means of the pocket structure, an impurity concentration at the central portion of the channel increases. This increases the threshold voltage of MISFET owing to the reverse short channel effect, resulting in the lowering of the current between the source and drain. This arises the problem that the drive ability of MISFET cannot be improved.
With the structure formed by combination of the pocket structure formed by obliquely implanting an impurity ion and the whole-area PTS structure, the formation of the whole-area PTS structure has to be formed, as set forth hereinabove, so that the impurity concentration in the semiconductor substrate, in which MISFET is to be formed, undesirably becomes high. Accordingly, the body-effect coefficient of the semiconductor substrate increases. This, in turn, results in the increase of space charge to lower a carrier density, so that the current between the source and drain lowers. This presents the problem that the drive ability of MISFET cannot be improved as well.
An object of the invention is to provide a technique of reliably suppress punch through in MISFET.
Another object of the invention is to provide a technique of improving the drive ability of MISFET.
The above and other objects and novel features of the invention will becomes apparent from the description of the specification and the accompanying drawings attached herewith.
Typical embodiments of the invention are briefly described below.
The invention provides a method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a gate electrode on a main surface of a semiconductor substrate and introducing an impurity of a second conduction type into the semiconductor substrate in the existence of the gate electrode to form a first semiconductor region of the second conduction type, implanting an impurity of a first conduction type vertically with respect to the main surface of the semiconductor substrate to form a second semiconductor region of the first conduction type at a lower portion of the first semiconductor region, implanting an impurity of the first conduction type obliquely relative to the main surface of the semiconductor substrate to form a third semiconductor region of the first conduction type between the first semiconductor region and the second semiconductor region, and after the formation of the third semiconductor region, introducing an impurity of the second conduction type into the semiconductor substrate to form a fourth semiconductor region of the second conduction type thereby forming MISFET, wherein a dosage of the impurity introduced upon the formation of the third semiconductor region is higher than a dosage of the impurity introduced upon the formation of the second semiconductor region.
The invention also provides a semiconductor integrated circuit device which comprises:
(a) MISFET having source-drain of an LDD structure made of a first semiconductor region of a second conduction type and a fourth semiconductor region of the second conduction type;
(b) a second semiconductor region of a first conduction type formed at a lower portion of the source-drain; and
(c) a third semiconductor region of the first conduction type formed at a region between the first semiconductor region and the second semiconductor region wherein a dosage of an impurity ion introduced into the third semiconductor region is relatively higher than a dosage of an impurity ion introduced into the second semiconductor region.
REFERENCES:
patent: 4701349 (1987-10-01), Koyanagi et al.
patent: 6541829 (2003-04-01), Nishinohara et al.
patent: 6552398 (2003-04-01), Hsu et al.
patent: 6586294 (2003-07-01), Post et al.
patent: 62-133712 (1990-03-01), None
patent: 2000-196079 (2000-07-01), None
Ichinose Katsuhiko
Mitani Shinichiro
Saito Tomohiro
Yanagida Youhei
Cuneo Kamand
Kilday Lisa
Miles & Stockbridge P.C.
Renesas Technology Corporation
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