Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reissue Patent
1998-09-25
2003-01-07
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S265000
Reissue Patent
active
RE037959
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and a method of manufacturing the same. More particularly, it relates to techniques which are effective when applied to a semiconductor integrated circuit device having a nonvolatile memory.
A nonvolatile memory cell of the one-element type has been proposed as the nonvolatile memory cell of an EEPROM (Electrically Erasable Programmable Read Only Memory). This nonvolatile memory cell is constructed of a field-effect transistor (MISFET) which has a floating gate electrode (information storing gate electrode) and a control gate electrode (controlling gate electrode). The source region of the MISFET is connected to a source line, and the drain region to a data line.
The nonvolatile memory cell is called a “flash type nonvolatile memory cell”, in which information is written with hot electrons and is erased by tunneling. More specifically, the information writing operation of the nonvolatile memory cell is carried out in such a way that hot electrons are generated by a high electric field in the vicinity of the drain region and are injected into the floating gate electrode. On the other hand, the information erasing operation of the nonvolatile memory cell is carried out in such a way that the electrons stored in the floating gate electrode are emitted into the source region by the Fowler-Nordheim type tunneling.
Since the area of the flash type nonvolatile memory cell can be reduced owing to the single-element type as stated above, the EEPROM configured of the cells has the feature that a larger memory capacity can be achieved.
By the way, the EEPROM mentioned above is explained in “1988 IEEE International Solid-State Circuits Conference”, pp. 132-133 and 330.
SUMMARY OF THE INVENTION
The inventor made studies on the EEPROM referred to above. As a result, the following problems have been revealed:
The dispersion of erasing characteristics is wide among the memory cells, and the number of times which each cell can be repeatedly rewritten is comparatively small, so that the reliability of the EEPROM is somewhat inferior.
The erasing characteristics depend greatly upon the shape of the floating gate electrode, especially the shape of the ends of this gate electrode. An electric field which is applied between the floating gate electrode and the source region in the erasing operation is as high as
10
8
[V/m] or above. Nevertheless, the electric field does not exhibit a uniform intensity distribution, but it tends to concentrate distortionally on the ends of the gate electrode, particularly the corners thereof, due to a so-called edge effect. Consequently, a slight dispersion in the shapes of the floating gate electrodes brings the erasing characteristics a wide dispersion.
Moreover, when the applied electric field in the erasing operation concentrates partially on any specific portion, the breakdown or degradation of an insulator film is liable to occur in the specific portion. This decreases the number of times which an erasing voltage is applied, namely, the number of times which the memory cell is repeatedly rewritten.
Besides, since the source region is formed by the process of ion implantation in self-alignment to the floating gate electrode as well as the control gate electrode, the overlap area between the source region and the floating gate electrode cannot be set sufficiently large. Therefore, a wide dispersion is caused in the erasing characteristics by a dispersion in the processing steps.
Further, the implantation of arsenic ions for forming the source region is performed through an insulator film, for example, thermal oxidation film which is formed on the front surface of a semiconductor substrate. On that occasion, a dangling bond is produced in the part of the oxide film corresponding to the end of the floating gate electrode. A leakage current ascribable to the dangling bond flows between the floating gate electrode and the source region, so that the withstand voltage between the floating gate electrode and the source region lowers to decrease the number of times which the memory cell is repeatedly rewritten. Moreover, such leakage currents cause the dispersion of the erasing characteristics among the memory cells.
An object of the present invention is to provide techniques that narrow the dispersion of erasing characteristics among memory cells and increase the number of times which each cell can be repeatedly rewritten, thereby to realize a nonvolatile memory of high reliability.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
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Komori Kazuhiro
Kume Hitoshi
Meguro Satoshi
Nishimoto Toshiaki
Yamamoto Hideaki
Booth Richard
Hitachi , Ltd.
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