Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Mesa formation
Reexamination Certificate
2001-11-16
2004-10-26
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Mesa formation
C438S187000, C438S149000
Reexamination Certificate
active
06808951
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof. The present invention particularly relates to a technique effectively applied to a semiconductor integrated circuit device including an electrically batch-erasable and rewritable nonvolatile semiconductor memory device (flash memory).
In a manufacturing process of a semiconductor integrated circuit device, when silicon oxide films deposited on a semiconductor substrate are etched to form contact holes, a means is taken to prevent a lower silicon oxide film exposed from each bottom portion of the contact holes, from being excessively etched. As the means, a technique is employed in which a silicon nitride film is provided between an upper layer and a lower layer of the silicon oxide films forming the contact holes, and only the upper layer of the silicon oxide films is etched by using the silicon nitride film as an etching stopper (as disclosed in, for example, Japanese Patent Laid-Open No. 11-26574, etc).
Also, in a manufacturing process of a recent mass storage DRAM (Dynamic Random Access Memory), when contact holes for connecting bit lines and capacitive elements to a semiconductor substrate are formed in spaces of gate electrodes fined, a self align contact (SAC) technique is employed (as disclosed by, for example, Japanese Patent Laid-Open No. 9-252098, etc.). The SAC technique forms the contact holes to be self-aligned to the spaces of the gate electrodes, by constituting an insulating film (referred to as a cap insulating film, a protection insulating film or the like) covering upper portions of the gate electrodes and an insulating film (sidewall insulating film) covering sidewalls of the gate electrodes by silicon nitride films, and by utilizing etching rate difference between the silicon oxide films and the silicon nitride films.
Further, in recent years, the above-mentioned SAC technique has gradually been employed in manufacturing processes of semiconductor memories other than the DRAM. For example, Japanese Patent Laid-Open No. 10-289951 discloses an invention in which the SAC technique is applied to a manufacturing process of an EEPROM (electrically erasable programmable read-only memory).
SUMMARY OF THE INVENTION
As a type among flash memories, there is known an NOR type flash memory. Each memory cell of the NOR type flash memory is provided between a gate oxide film and a control gate electrode (word line) located on an upper portion thereof, and is constituted by a so-called floating gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a floating gate electrode electrically insulated from the periphery thereof is used as a charge accumulation region. A floating gate type MISFET can relatively reduce a memory size since a control gate electrode (word line) is laminated on an upper portion of a floating gate electrode formed through a thin gate insulating film formed on a main surface of a semiconductor substrate. It can be, therefore, said that the floating gate type MISFET has a memory cell structure suitable for realizing a mass storage.
In the case of the above-mentioned NOR type flash memory, there is a typical method for operation of being written into a memory cell. As the typical method, electrons are injected into the floating gate electrode, and threshold voltage (Vth) of a transistor by using a control gate electrode as a reference voltage is raised in comparison with a state in which no electrons thereof are accumulated. Injection of electrons into the floating gate electrode has, as typical methods, two systems. There is one system in which, by changing a channel current flowing in a source and drain channel to hot electrons in the vicinity of a drain, an electric field of the control gate electrode biased to have a positive voltage makes the hot electrons drown into the floating gate electrode. As another example, there is the other system in which, by a positive voltage applied to a control gate electrode, hot electrons generated by avalanche breakdown in the vicinity of a drain thereof are drown into a floating gate electrode. On the other hand, as a typical example of an erasing operation, there is utilized a system in which, by making electrons FN tunneling (Fowler-Nordheim tunneling) into a gate insulating film below a floating gate electrode, the electrons which are accumulated in the floating gate electrode, the electrons are discharged into the source or drain region of the semiconductor substrate.
Further, in the NOR type flash memory, memory cells are arranged in a lattice shape at respective intersections between predetermined number of word lines extending parallel to one direction and predetermined number of data lines extending parallel to a direction orthogonal to these word lines, the data lines are connected to drain regions of a MISFET constituting each memory cell, and source lines are connected to source regions thereof, respectively. Therefore, if each size of the memory cells is fined in order to make the NOR type flash memory mass storage, then the above-stated SAC technique is indispensable to formation of contact holes for connecting the data lines to the drain regions and that of contact holes for connecting the source lines to the source regions.
However, in the case where the SAC technique is introduced into flash memory manufacturing processes in order to form an insulating film protecting the upper portions of the control gate electrodes out of a silicon nitride film, a silicon nitride film over a control gate electrode gives high stress to a gate oxide film and a substrate of a lower portion thereof and causes crystal defects in the gate oxide film. As a result, it has become clear from consideration of the inventors of the present invention that there arises a problem peculiar to the floating gate type MISFET, the problem being one that charges accumulated in the floating gate electrode easily leak into the substrate.
Taking this disadvantage into account, the inventors of the present invention has considered realization of micro-fabrication memory cell using the SAC technique during suppression of the stress relative to the gate oxide film and the substrate of the lower portion thereof, by forming the protection insulating film over a control gate electrode by a silicon oxide film instead of a silicon nitride film or by a laminating film formed of a silicon oxide film and a silicon nitride film, and then by forming a sidewall insulating film by a silicon nitride film.
However, it has become clear that there arise the following problems of a MISFET manufacturing process in the case of forming the protection insulating film over the control gate electrode by a silicon oxide film. These problems will be described with reference to
FIGS. 45
to
50
.
To form a MISFET having two-layer gate structure consisting of a floating gate electrode and a control gate electrode, first, a polycrystalline silicon film
102
A, an ONO film
103
, a polycrystalline silicon film
104
A, and a silicon oxide film
105
are sequentially deposited on a gate oxide film
101
formed on the main surface of a semiconductor substrate
100
in this order, as shown in FIG.
45
. The polycrystalline silicon film
102
A is used for a floating gate. The ONO film
103
consists of a silicon oxide film, a silicon nitride film and a silicon oxide film. The polycrystalline silicon film
104
A is used for a control gate. The silicon oxide film
105
is served as a protection insulating film.
Next, as shown in
FIG. 46
, by using a photoresist film
106
as a mask, the silicon oxide film
105
is dry-etched. After the photoresist film
106
is removed, as shown in
FIG. 47
, the polycrystalline silicon film
104
A, the ONO film
103
and the polycrystalline silicon film
102
A which are located below the silicon oxide film
105
are sequentially dry-etched by using the silicon oxide film
105
as a mask. Thereby, floating gate electrodes
102
consisting of the polycrystalline silicon film
Ikeda Yoshihiro
Okada Daisuke
Okazaki Tsutomu
Tsukamoto Keisuke
Yanagita Hiroshi
Jr. Carl Whitehead
Miles & Stockbridge P.C.
Schillinger Laura M
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