Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2003-06-12

2004-09-21

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S185250, C365S189011, C365S205000

Reexamination Certificate

active

06795358

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and to a technology effective for application to a semiconductor integrated circuit device equipped with a memory circuit.
It has been reported from the result of a known-example search subsequent to the completion or achievement of the invention of the present application that as ones related to such complementary bit-line precharge as described in the invention of the present application, there have been provided (1) gate boost precharge, (2) Unexamined Patent Publication No. 2000-100171 cited or listed below as a Patent Document 1, and (3) Unexamined Patent Publication No. Hei 10 (1998)-178161 cited or listed below as a Patent Document 2. (1) is intended to boost the gate of a precharge MOS transistor to VPP (word line voltage) to thereby speed up a precharge operation for the purpose of speeding up of bit line precharge. (2) is intended to dispose only a short MOS transistor of a precharge circuit outside a shared MOS transistor to thereby speed up a precharge operation for the purpose of speeding up of bit line precharge. (3) aims to reduce a threshold voltage of a transistor of a precharge circuit to thereby speed up a precharge operation for the purpose of speeding up of bit line precharge.
Patent Document 1:
Unexamined Patent Publication No. 2000-100171
Patent Document 2:
Unexamined Patent Publication No. Hei 10 (1998)-178161
SUMMARY OF THE INVENTION
In the above technology of (1), power consumption of a generator for generation of a word line voltage (VPP) used as a start signal of a short MOS transistor increases. Since a mat activation rate of a high-speed mixed DRAM intended for, for example, a cache memory or the like becomes even twenty times that of a general purpose DRAM, current consumption based on VPP for boosting the gate of the precharge MOS transistor reaches even 2A or more according to a trial calculation made by the inventors or the like of the present application. Although the above technology of (2) (Patent Document 1) has described that “a control signal for the short MOS transistor is reduced to a voltage less than or equal to a shared MOS transistor control signal to thereby achieve low power consumption”, such consideration that a “thin-film transistor” is used for the short MOS transistor and its level is reduced to a bit line voltage level”, is not paid. The present technology has no description about a layout shape of the short MOS transistor per se and its layout method. Although the above technology of (3) (Patent Document 2) describes that “a two-dimensional form or the like of a precharge transistor is varied to reduce a threshold voltage thereof”, there is no consideration that the voltage of a control signal itself is reduced to achieve low power consumption.
An object of the present invention is to provide a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a representative one of the inventions disclosed in the present application will be described in brief as follows: At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.


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patent: 10-178161 (1996-12-01), None
patent: 11-31794 (1997-07-01), None
patent: 11-086529 (1997-09-01), None
patent: 2000-100171 (1998-09-01), None

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