Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-21
2006-11-21
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S700000, C714S817000
Reexamination Certificate
active
07139952
ABSTRACT:
A semiconductor integrated circuit having a plurality of wirings and a scan chain including a testing circuit configured to detect glitch noise caused by crosstalk between the wirings and a plurality of scan flip-flops connected in series, the semiconductor integrated circuit includes a retention circuit receiving a data signal propagating a test-subject wiring, and a detection circuit receiving the data signal and an output signal of the retention circuit, detecting glitch noise occurring in the data signal, and delivering an output signal to the retention circuit.
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patent: 6594805 (2003-07-01), Tetelbaum et al.
patent: 6907590 (2005-06-01), Al-Dabagh et al.
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patent: 2002/0124218 (2002-09-01), Kishimoto
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Matsumoto Takashi
Oiso Masaki
DLA Piper (US) LLP
Kabushiki Kaisha Toshiba
Tu Christine T.
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