Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-09-26
2009-08-18
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S005110, C714S006130, C714S006130, C714S042000, C714S054000, C714S710000, C714S719000, C714S711000, C714S743000, C365S201000
Reexamination Certificate
active
07577885
ABSTRACT:
A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.
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Y. Onozaki “Design Testability of the System LSI” from Design Wave Magazine, CQ Publishing Co.. Ltd. Aug. 2002. Partial English translation of relevant pages (Japanese version submitted Sep. 26, 2006).
Hasegawa Tetsu
Tokunaga Chikako
Banner & Witcoff LTD
Kabushiki Kaisha Toshiba
Trimmings John P
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