Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-01-24
2004-10-26
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C327S276000
Reexamination Certificate
active
06810497
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit compensating variations of delay time and, more particularly, to a technique for compensating variations of delay time cause by an input signal pattern.
(b) Description of the Related Art
In a semiconductor device, the circuit specification is generally limited by a delay time for signal processing. Especially, the circuit specification is limited by a largest delay time among the delay times for signal processing based on a variety of input signal patterns.
Referring to
FIG. 1
, a conventional semiconductor integrated circuit includes an internal circuit
101
, input flip-flops
103
, and a source potential reduction circuit
102
, wherein the input flip-flops
103
receive input data IN
1
, which have various signal patterns, through input signal lines
104
to deliver the input data to the internal circuit
101
. The internal circuit
101
acts as a functional circuit, which operates therein for processing the input data IN
1
to deliver output data through the output signal lines
105
after the processing. The internal circuit
101
may be called a functional circuit.
The power source potential Vint is supplied to the internal circuit
101
from the source potential reduction circuit
102
which generates a reduced potential for the source potential Vint and delivers the same through an internal source line
106
for achieving alleviation of the electric field and reduction of the power dissipation in the internal circuit
10
. The reduced source potential Vint allows reduction of the dimensions of the semiconductor elements in the internal circuit
101
, whereby the semiconductor integrated circuit has a lower power dissipation and a reduced occupied area thereof as well as a higher operational reliability of the internal circuit
101
.
In general, a higher internal source potential allows a higher operational speed in an LSI (large-scaled integrated circuit). In the case of the internal circuit
101
being implemented by a static circuit having CMOS transistors, the power dissipation of the internal circuit is expressed by C Vint×Vint/2 wherein C is the sum of the load capacitances of the internal circuit. Thus, by reducing the internal source potential Vin, the power dissipation can be effectively reduced irrespective of some power dissipation caused in the source potential reduction circuit
102
. The source potential reduction circuit
102
may be provided outside the chip of the semiconductor integrated circuit as a power IC (integrated circuit) or a DC—DC (direct current-direct current) converter.
The internal circuit
101
outputs the results of the processing therein based on input signal patterns, and the delay of the internal circuit
101
or the operational speed thereof depends on the input signal patterns IN
1
received therein.
For example, if the input data IN
1
are address signals for a semiconductor memory device such as shown in
FIG. 2
, the input signal patterns IN
1
specify the locations of the memory cells accessed by the input signal patterns in the chip of the memory device. In this case, the read time for the memory cells depends on the distance of the signal path between the input/output section
111
and the accessed memory cells.
More specifically, the semiconductor memory device of
FIG. 2
includes a plurality of memory banks
114
to
121
, each of which includes a plurality of memory cells arranged in a matrix. Each of the memory cells is connected to a bus line such as
132
and
134
via an in-bank line such as
133
and
135
. The bus lines
132
and
134
are connected to an ECC (error correcting code) section
112
directly or via signal line
131
, which pass through a control circuit section (CCS)
113
.
The ECC section
112
is connected to an input/output (I/O) section
111
, which functions as interface with external circuits.
The I/O lines
136
corresponds to both the input signal line
104
and the output signal line
105
in
FIG. 1
, and the flip-flops
103
correspond to a part of the I/O section
111
. The potential reduction circuit
112
corresponds to a part of the control circuit section
113
, and the rest of the constituent elements in
FIG. 1
is included in the internal circuit
101
.
In operation, the address signal supplied through the I/O section
111
passes the ECC section
112
, and is decoded in the control circuit section
113
. More specifically, the most significant three bits of the address signals specify one of the eight memory banks
114
to
121
, and the next significant fourth bit specifies one of the pair of half sections in each memory bank. The remaining less significant bits specify the address of the desired memory cells in each half section in each memory bank by using a row decoder and a column decoder. The read data from the specified memory cells include redundancy data for an error correction as well as the data stored in the specified memory cells.
The read data are transferred from the in-bank signal lines
133
or
135
, via the bus lines
132
or
134
after amplification thereof, to the ECC section
112
. The read data from the far memory banks
118
to
121
are transferred additionally via signal lines
131
which pass through the control circuit section
113
. The ECC section
112
operates for an error correction processing based on the redundancy data, and outputs the read data to the I/O section
111
after the error correction. The I/O section
111
delivers the read data outside the memory device via the I/O lines
136
.
The travel distance both for input address signals to reach selected memory cells and for the read data to be output depends on the input address patterns, whereby the access time with selected memory cells follows the exemplified graph shown in FIG.
3
. Each of the input addresses shown therein includes most significant four bits which specify the memory bank as well as the half section thereof and the other less significant bits which specify the memory cell therein. Abrupt changes in the graph are due to the difference in the path length between the half section of the memory bank and the I/O section
111
, whereas the gradual (upward) change between the adjacent abrupt changes is due to the difference in path length between the memory cells in each half section of each memory bank.
The dependency of the access time on the input address pattern shown in
FIG. 3
follows the configuration of the memory banks
114
to
121
, location or arrangement of the I/O section
111
, the material or structure of the signal lines such as
131
, electric characteristics of the transistors for driving the signal lines etc. The variation of the delay time depending on the input signal pattern is inevitable because all the memory cells cannot be located at a single position. Thus, the maximum delay time t
max
, as shown in
FIG. 3
, is considered to represent the performance of the overall circuit.
The variations of the delay time due to the input signal patterns also result from, in addition to the different path lengths, a different speed at which each instruction is executed by such circuits as CPU (central processing unit), MPU (micro processing unit), DSP (digital signal processor) or so on which interprets a variety of commands and executes the interpreted command in case by case. In the processor, such simple instructions as logical operation coexist with such complicated instructions as multiplication. This fact causes large difference of delay times depending on input commands. In specification, delay time of each command is raised to agree with one—several fold clock cycles, therefore a fractional difference of delay time remains to be compensated by this invention.
“IEEE JOURNAL OF SOLID-STATE CIRCUITS”, VOL. 25, October, 1990, pp1136-1140 describes a compensating circuit for compensating the variations of the delay time by using a phase locked loop.
FIG. 4
shows the described compensating circuit used for an internal circuit
1
Dooley Matthew C.
Lamarre Guy J.
NEC Electronics Corporation
Young & Thompson
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