Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-02-28
2009-12-29
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07640473
ABSTRACT:
A semiconductor integrated circuit apparatus includes an internal logic circuit unit, a first memory, a second memory and a control circuit unit. The internal logic circuit unit includes scan chains which test circuit normality. The first memory is accessed by the internal logic circuit. The second memory stores valid bits associated with the first memory, wherein the valid bits indicates one of validity and invalidity of data stored in the first memory. The control circuit unit saves internal state data stored in the scan chains to the first memory, and resets the internal state data saved in the first memory to the scan chains.
REFERENCES:
patent: 6370664 (2002-04-01), Bhawmik
patent: 2004/0153762 (2004-08-01), Flynn et al.
patent: 6-052070 (1994-02-01), None
Chung Phung M
Foley & Lardner LLP
NEC Electronics Corporation
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