Semiconductor integrated circuit and testing method thereof

Details Semiconductor integrated circuit and testing method thereof Semiconductor integrated circuit and testing method thereof

2007-05-22

2007-05-22

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S702000

Reexamination Certificate

active

10430319

ABSTRACT:
There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

REFERENCES:
patent: 4484303 (1984-11-01), Provanzano et al.
patent: 6336088 (2002-01-01), Bauman et al.
patent: 6587979 (2003-07-01), Kraus et al.
patent: 11-250698 (1998-03-01), None
patent: 2000-111618 (1998-09-01), None

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