Semiconductor integrated circuit and system LSI having a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S733000, C714S738000

Reexamination Certificate

active

07739571

ABSTRACT:
In a semiconductor integrated circuit11, there is constructed a test expected value programming circuit100having an input/input-output pad103for retrieving a ground/power-source signal104from a ground terminal30or a power source terminal31connected to the semiconductor integrated circuit11, a switch105for selectively switching the outputting of the ground/power-source signal104inputted via the input/input-output pad103, and an expected value generation circuit13for generating a test expected value signal21based on a switch output signal122outputted from the switch105.

REFERENCES:
patent: 5933434 (1999-08-01), Roohparvar
patent: 6708301 (2004-03-01), Ohta et al.
patent: 7000160 (2006-02-01), Tanaka et al.
patent: 2003/0237036 (2003-12-01), Kimura
patent: 56-11369 (1981-02-01), None
patent: 5-26979 (1993-02-01), None
patent: 06-043222 (1994-02-01), None
patent: 6-43222 (1994-02-01), None
patent: 6-194423 (1994-07-01), None
patent: 2000-266816 (2000-09-01), None
patent: 2003-114259 (2003-04-01), None
patent: 2004-93421 (2004-03-01), None
Japanese Office Action, with English translation, issued in Japanese Patent Application No. 2007-500418, mailed Aug. 25, 2009.

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