Semiconductor integrated circuit and semiconductor memory...

Details Semiconductor integrated circuit and semiconductor memory... Semiconductor integrated circuit and semiconductor memory...

2000-02-09

2001-05-22

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S206000, C365S207000, C365S189090

Reexamination Certificate

active

06236605

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which includes a sense amplifier for amplifying a weak signal.
In addition, the present invention relates to a semiconductor memory device such as DRAMs, and more particularly to a semiconductor memory device including an overdriving sense amplifier.
2. Description of the Related Art
Not only a large memory capacity, but also a low power consumption and a high speed operation are increasingly required of a dynamic random access memory (DRAM).
Besides, in general, an integrated circuit such as semiconductor memory has a sense amplifier for amplifying data read out of a memory cell.
FIG. 1
shows an outline of a memory core unit of DRAMs.
A plurality of rectangular memory cell arrays
2
are arranged in the memory core unit
1
. Each of the memory cell arrays
2
is configured of a plurality of memory cells MC which are arranged vertically and horizontally. The memory cell arrays
2
are surrounded with sense amplifier rows
3
and sub word decoder rows
4
which are respectively arranged in the horizontal direction and vertical direction. Sense amplifier drivers
5
are arranged in regions in which the sense amplifier rows
3
and the sub word decoder rows
4
intersect (regions which confront the four corners of the memory cell arrays
2
).
Word lines WL (hereinbelow, also individually termed “word lines WL
0
and WL
1
”) are connected to the memory cell arrays
2
, arranged from the sub word decoder rows
4
on the upper sides of the memory cell arrays
2
as viewed in the figure. Besides, bit lines BL and BLB are connected to the memory cell arrays
2
, and they are arranged alternately from the sense amplifier rows
3
on both the sides of the memory cell arrays
2
as viewed in the figure. The bit lines BL and BLB are complementary bit lines in which, when one of them is used for reading data, the other is set at a reference voltage. The sense amplifier rows
3
are controlled by the sense amplifier drivers
5
on the upper sides of these sense amplifier rows as viewed in the figure.
FIG. 2
shows the details of the memory core unit
1
and a peripheral circuit unit
15
.
Each of the sense amplifier rows
3
includes a plurality of sense amplifiers AMP, precharging circuits
6
, and nMOS transistors
7
a
,
7
b
,
7
c
,
7
d
. The bit line BL is connected to the corresponding sense amplifier AMP through the nMOS transistors
7
a
,
7
b
. On the other hand, the bit line BLB is connected to the corresponding sense amplifier AMP through the nMOS transistors
7
c
,
7
d
. A controlling signal BT
1
is applied to the gates of the nMOS transistors
7
a
,
7
c
, while a controlling signal BT
2
is applied to the gates of the nMOS transistors
7
b
,
7
d.
The sense amplifier AMP has two CMOS inverters
8
,
9
. The input nodes and output nodes of the CMOS inverters
8
,
9
are interconnected. A sense amplifier driving signal VP is applied to the sources of pMOS transistors
8
a
,
9
a
constituting the respective CMOS inverters
8
,
9
. Also, a sense amplifier driving signal VN is applied to the sources of nMOS transistors
8
b
,
9
b
constituting the respective CMOS inverters
8
,
9
. The output nodes of the CMOS inverters
8
,
9
are respectively connected to the bit lines BL, BLB. By the way, in the following description, a pMOS transistor and an nMOS transistor shall be simply termed “pMOS” and “nMOS”, respectively.
In order to operate the plurality of sense amplifiers AMP at high speed, wiring patterns for the sense amplifier driving signals VP, VN are widened, so that they have large load capacitance.
The precharging circuit
6
has the bit lines BL and BLB connected thereto, and is fed with a precharging signal PR and a precharged voltage VPR. The precharged voltage VPR is a voltage which is equal to one half of an internal supply voltage Vii. The precharging circuit
6
is a circuit which supplies the precharged voltage VPR to the bit lines BL, BLB, and which equalizes the bit lines BL, BLB.
The word lines WL
0
, WL
1
are respectively connected to the gates of the cell transistors TR
0
, TR
1
(both being nMOS's) of the memory cells MC
0
, MC
1
. The bit lines BL, BLB are respectively connected to the sides of the cell transistors TR
0
, TR
1
opposite to the cell capacitors of the memory cells MC
0
, MC
1
.
The sense amplifier driver
5
includes a pMOS
11
, the gate of which is fed with a sense amplifier activating signal SAB. The sense amplifier driving signal VP is outputted from the drain of the pMOS
11
. Also included is an nMOS
14
, the source of which is supplied with a ground voltage VSS. A sense amplifier activating signal SA is applied to the gate of the nMOS
14
. The sense amplifier driving signal VN is outputted from the drain of the nMOS
14
. The precharging signal PR is applied to the gates of nMOS's
12
,
13
which are located centrally in the sense amplifier driver
5
. The precharged voltage VPR is supplied to the source of the nMOS
12
and the drain of the nMOS
13
.
The pMOS
11
and the nMOS
14
supply the internal supply voltage Vii and the ground voltage VSS to the respective sense amplifier driving signals VP, VN of large load capacitance, and they have high drivability in order to operate the plurality of sense amplifiers AMP at high speed. Consequently, the sizes of the pMOS
11
and the nMOS
14
are large.
On the other hand, the peripheral circuit unit
15
has a timing generator
16
, a PR generator
17
for generating the precharging signal PR, and an SA generator
18
for generating the sense amplifier activating signals SA, SAB. This peripheral circuit unit
15
is formed in a region outside the memory core unit
1
shown in FIG.
1
. Besides the above circuits
16
,
17
and
18
, pads, an input/output buffer, a main word decoder, a column decoder, or the like, which are not shown, are arranged in the peripheral circuit unit
15
.
The timing generator
16
generates and outputs a precharging timing signal PRT which controls the precharging timing of the bit lines BL, BLB, and a sense amplifier timing signal SAT which controls the driving timing of the sense amplifier AMP.
The PR generator
17
receives the precharging timing signal PRT and a decoding signal WDEC of row addresses, and outputs the precharging signal PR which becomes a low level at the activation of the sense amplifier AMP.
The SA generator
18
receives the sense amplifier timing signal SAT and the decoding signal WDEC, and outputs the sense amplifier activating signals SAB, SA.
FIG. 3
shows the details of the SA generator
18
.
The SA generator
18
is configured of a logic circuit
19
and four CMOS inverters
20
,
21
,
22
, and
23
. The logic circuit
19
is fed with the decoding signal WDEC and the sense amplifier timing signal SAT, and outputs signals SAB
0
, SA
0
for activating the sense amplifier AMP. The activating signals SAB
0
, SA
0
are signals whose phases are inverted from each other. The internal supply voltage Vii and the ground voltage VSS are respectively supplied to the sources of the pMOS's
20
a
,
21
a
,
22
a
,
23
a
and nMOS's
20
b
,
21
b
,
22
b
,
23
b
of the CMOS inverters
20
,
21
,
22
,
23
. The CMOS inverter
20
receives the activating signal SAB
0
through the CMOS inverter
23
, and outputs the received signal as the sense amplifier activating signal SAB. Likewise, the CMOS inverter
21
receives the activating signal SA
0
through the CMOS inverter
22
, and outputs the received signal as the sense amplifier activating signal SA. The sense amplifier activating signals SAB and SA are signals which become a low level and a high level at the activation of the sense amplifier AMP, respectively.
In the DRAM described above, for example, a read cycle is performed in order to read out data of high level written in the memory cell MC
0
shown in FIG.
2
.
FIG. 4
shows the timings of the principal signals in the read cycle.
Before the read cycle, the precharging signal PR is at a hig

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