Semiconductor integrated circuit and scan test method therefor

Details Semiconductor integrated circuit and scan test method therefor Semiconductor integrated circuit and scan test method therefor

2008-07-15

2008-07-15

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C714S699000

Reexamination Certificate

active

10763255

ABSTRACT:
A method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested. The method includes isolating each of the at least two blocks to be tested exclusively from further blocks; and supplying a plurality of scan clocks having different phases each to each of the at least two blocks. In addition, a semiconductor integrated circuit includes at least two blocks to be tested, an Core Wrapper Architecture isolation unit for isolating each of the at least two blocks to be tested exclusively from further blocks, and an input terminal for inputting a plurality of scan clocks each to each of the at least two blocks, in which a Wrapper register included in the Core Wrapper Architecture is configured to be supplied selectively with one of a scan clock and a system clock for the blocks.

REFERENCES:
patent: 5805608 (1998-09-01), Baeg et al.
patent: 5812562 (1998-09-01), Baeg
patent: 6018815 (2000-01-01), Baeg
patent: 6021513 (2000-02-01), Beebe et al.
patent: 6587979 (2003-07-01), Kraus et al.
patent: 6654920 (2003-11-01), Hetherington et al.
patent: 6957403 (2005-10-01), Wang et al.
patent: 2003/0204802 (2003-10-01), Sim
patent: 10-242283 (1998-09-01), None
patent: 2000-115147 (2000-04-01), None
patent: 2000-261310 (2000-09-01), None
patent: 2000-332733 (2000-11-01), None
patent: 2002-56044 (2002-02-01), None
patent: 2002-203001 (2002-07-01), None
“A Token Scan Architecture for Low Power Testing”, p. 660, Proc. International Test Conference 2001, Oct. 30, 2001, Baltimore, MD USA.

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit and scan test method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit and scan test method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and scan test method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3929972