Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2010-05-26
2011-11-08
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S731000
Reexamination Certificate
active
08055965
ABSTRACT:
A semiconductor integrated circuit includes: a plurality of scan flip-flops configured to form a scan chain in a scan test; and a plurality of clock gating circuits connected between a clock input and corresponding portions of the plurality of scan flip-flops, respectively. The plurality of clock gating circuits are connected in serial to form a chain and gating setting data is inputted in serial through the chain connection. Each of the plurality of clock gating circuits controls a connection between the clock input and a corresponding portion of the plurality of scan flip-flops based on the gating setting data.
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McGinn Intellectual Property Law Group PLLC
Renesas Electronics Corporation
Tabone, Jr. John J
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