Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-05-25
2010-06-22
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S005110, C714S042000, C714S724000, C714S726000, C714S731000, C714S733000, C714S734000, C714S736000, C714S742000, C714S744000, C365S201000
Reexamination Certificate
active
07743301
ABSTRACT:
A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a manner that the MISR is caused to operate at a high-speed clock when the compressed data is generated and stored, and at a low-speed clock when the stored compressed data is read out and output.
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McGinn IP Law Group PLLC
NEC Electronics Corporation
Trimmings John P
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