Semiconductor integrated circuit and method for testing the...

Details Semiconductor integrated circuit and method for testing the... Semiconductor integrated circuit and method for testing the...

2005-11-29

2005-11-29

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S724000

Reexamination Certificate

active

06971052

ABSTRACT:
When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.

REFERENCES:
patent: 5119335 (1992-06-01), Nozaki
patent: 5514991 (1996-05-01), Uehara et al.
patent: 5751944 (1998-05-01), Roohparvar et al.
patent: 2002/0178414 (2002-11-01), Roohparvar
patent: 2001-243796 (2001-09-01), None
patent: 2001-243797 (2001-09-01), None

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