Semiconductor integrated circuit and method for testing same

Details Semiconductor integrated circuit and method for testing same Semiconductor integrated circuit and method for testing same

2003-08-26

2009-02-03

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07487418

ABSTRACT:
An LSI which makes scan testing possible without compromising security is provided. Flip-flops that constitute a scan chain are reset when scan testing is initiated or terminated by the edges of a mode signal for switching between normal operations and scan testing. In addition, during scan testing, internal memory means is made inaccessible. Further, a dummy flip-flop that operates only during scan testing is connected to the scan chain, and shifting out by the scan chain during normal operations is made impossible.

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