Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2002-05-13
2002-12-24
Le, Son Phu (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S093000, C716S030000
Reexamination Certificate
active
06498515
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit that is less affected by performance degradation of transistors with time, and also relates to a method for designing such a circuit.
Recent dramatic downsizing of semiconductor integrated circuits have caused various problems. As for transistors, a latch-up phenomenon and hot carrier effects are typical examples of those problems encountered often.
The hot carrier effects refer to a phenomenon in which greatly energetic electrons (which are also called “hot electrons”) cross the junction of a semiconductor to enter the gate oxide of a transistor. After having entered the gate oxide, those hot electrons are trapped and accumulated in the oxide, thus increasing the threshold voltage of the transistor. As a result, the drivability of the current decreases. The longer the cumulative operation time of a transistor, the more degraded the transistor and the lower its operating speed become due to the hot carrier effects.
This degradation phenomenon is possibly retarded either by weakening the electric field within the channel or by reducing the current flowing through the transistor. In general, as a transistor is downsized, the supply voltage tends to decrease. However, since the effective channel length Leff also becomes shorter correspondingly, the electric field within the channel does not always weaken. Also, it would not be advantageous either to reduce the current flowing through the transistor. This is because the drivability of the transistor and the performance of an LSI, including that transistor, would both decline.
For further details of physical phenomena like these, see “Circuits, Interconnections and Packaging for VLSI”, Addison-Wesley Publishing Company, Inc.
In the prior art, the performance degradation of a transistor due to hot carrier effects has been estimated on a transistor-by-transistor basis. For example, transistors with degraded performance are spotted by incorporating a hot carrier effect degradation model into a circuit simulator (see, e.g., Japanese Laid-Open Publication No. 1-94484). According to another technique, the stress dependence of indices in a degradation rate equation is obtained, thereby simulating degradation due to the hot carrier effects under an AC stress (see, e.g., Japanese Laid-Open Publication No. 7-99302).
In the currently available timing simulation technique for logic circuits, the logic circuits are tested on the assumption that the performance of the logic circuits would not degrade with time. Actually, though, the transistors do degrade due to the hot carrier effects, and therefore, degradation of the logic circuits is also unavoidable. For example, delays of the logic circuits increase with time.
Particularly when a logic circuit on a critical path degrades after a long-time use, the performance of the entire circuit cannot be ensured even if proper operation thereof is ensured in its initial state. Thus, logic circuits should also be designed while taking future degradation thereof into account.
In addition, a degraded logic circuit also causes a problem in delivering a clock signal. In recent years, a gated clocking technique is often adopted for an LSI to reduce the power dissipation thereof. That is to say, where just a part of an LSI has to be operated, if a clock signal is delivered to the other unneeded part of the LSI, power is wasted by the clock delivery circuit in vain. Thus, according to the gated clocking technique, the clock delivery circuit is provided with a circuit for selectively delivering the clock signal to only the necessary part of an LSI.
FIG.
16
(
a
) illustrates a conventional technique of delivering a clock signal. As shown in FIG.
16
(
a
), a clock signal is always delivered from a clock signal source to both circuits A and B. In this case, the signal delivered to the circuits A and B changes its level the same number of times and therefore both of these circuits A and B degrade to the same degree. Thus, even after these circuits A and B have degraded with time, the clock skew between internal clock signals for the circuits A and B does not increase.
FIG.
16
(
b
) illustrates a gated clocking technique. An AND circuit
73
is inserted as a clock controller between a circuit for delivering a clock signal to the circuit A and the circuit A. In response to a control signal input, the AND circuit
73
may stop delivering the clock signal to the circuit A. At a point in time, the total numbers of times the clock signal delivered to the circuits A and B has changed its level may be 10
14
and 10
16
, respectively. In such a situation, the circuit B degrades at a higher rate and causes a longer delay than the circuit A. As a result, the clock skew between the internal clock signals for the circuits A and B increases after these circuits have degraded with time.
Furthermore, a clock net is generally implemented as a clock tree, in which degradation rates are also variable among the clock controllers for respective branches. Accordingly, after a long time has passed, the clock skew may also increase for that reason.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide (1) a semiconductor integrated circuit that is less affected by performance degradation with time by implementing transistors in such a configuration as suppressing the degradation due to hot carrier effects, and (2) a method for designing such a circuit.
Specifically, an inventive semiconductor integrated circuit includes a complementary metal oxide semiconductor (CMOS) logic circuit with multiple input terminals. The CMOS logic circuit includes a plurality of serial connections of n-channel transistors. The serial connections are connected in parallel to each other between an output terminal and a ground line. In every one of the serial connections, each said input terminal is connected to the gate of at least one of the n-channel transistors. And in at least one of the serial connections, the input terminal is connected to the gate of one of the n-channel transistors that is more distant from the output terminal than another one of the n-channel transistors that is closest to the output terminal is.
According to the present invention, none of the input terminals of the CMOS logic circuit is connected to ONLY the n-channel transistors that are closest to the output terminal and most likely to degrade. Thus, there is no path in which a delay from the input terminal to the output terminal changes significantly due to degradation of the transistors.
In one embodiment of the present invention, each said input terminal is connected to the gate of one of the n-channel transistors in every one of the serial connections so as to minimize a maximum sum of degradation rates of the n-channel transistors that are connected to the same input terminal.
In such an embodiment, it is possible to average the rates of increase in delay time caused by the paths from respective input terminals to the output terminal due to degradation with time. Thus, none of the paths increases the delay time outstandingly.
An inventive logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path co
Iwanishi Nobufusa
Kawakami Yoshiyuki
Le Son Phu
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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