Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-06
2003-01-28
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S253000, C438S396000
Reexamination Certificate
active
06511877
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same and, more particularly, to a large scale integrated circuit (LSI) including a nonvolatile ferroelectric random access memory cell (FRAM cell) having an array of nonvolatile ferroelectric random access memory (FRAM) cells using a ferroelectric film as a capacitor insulation film and a method for manufacturing the same.
An FRAM cell is constituted by replacing a capacitor of DRAM cell with a ferroelectric capacitor and operated using a method of taking charges in polarization inversion or noninversion out of the ferroelectric capacitor through a switching MOS transistor (data destructive read). The FRAM cell is featured in that data stored in a memory cell is not lost even when an operating power is turned off.
As compared with a DRAM representing a large capacity memory, the FRAM has the feature of dispensing with both a refresh operation for data retention and power consumption in a standby mode since it is nonvolatile. As compared with a flash memory of another nonvolatile memory, the FRAM has the feature of increasing the number of times of data rewriting and in that a data rewrite speed is fast. Moreover, as compared with an SRAM used for a memory card and the like and requiring the backup of a battery, the FRAM has the feature of decreasing power consumption and greatly reducing cell area.
Since the FRAM having the above features can be operated at high speed without any battery, it is going to be applied to a noncontact card such as RF-ID (Radio Frequency-Identification). There is a great hope that the FRAM will be replaced with the existent DRAM, flash memory and SRAM and applied to a mixed device such as a logic circuit.
In order to manufacture an FRAM, a ferroelectric capacitor having a stacked structure of a lower electrode, a ferroelectric film and an upper electrode is formed on an underlying insulation film, and metal wiring such as Al and Cu is provided through a contact hole formed in an oxide film on the stacked structure, thereby to protect the ferroelectric capacitor using a passivation film.
As described above, the FRAM cell can be increased in speed and decreased in power consumption, and a high degree of integration thereof is expected. It is thus necessary to consider a manufacturing process which reduces the area of memory cells and hardly degrades the ferroelectric materials.
In the existent FRAM device, a multilayer wiring technique, which is essential to a high degree of integration and a mixture of the other devices such as a DRAM and logic, has not yet been established.
One reason making it hard to achieve a high degree of integration and form a multilayer wiring layer of an LSI mounted with an FRAM device, is a difficulty in fine dry etching technique for capacitors.
As illustrated in
FIG. 1
, in the fine dry etching of a capacitor, especially in forming a Pt electrode
101
used as a capacitor electrode on a semiconductor substrate
100
, a resist pattern
102
, which is to be used in the photolithographic process, is prepared and Pt
101
′ is processed by reactive ion etching (RIE). Thus, a residue (fence)
103
will be formed and in the subsequent process it cannot be removed, which is a serious problem in miniaturization.
Another reason making it hard to achieve a high degree of integration and multilayer wiring of an LSI mounted with an FRAM device, is that the ferroelectric material used for a capacitor is very weak in reduction atmosphere (especially hydrogen atmosphere). In most of the existent LSI processes, hydrogen is mixed. To fill a via of a multilayer wiring structure, especially a via having a large aspect ratio, chemical vapor deposition (CVD) is used mainly and tungsten (W) is buried in the via. Since, however, hydrogen is generated in the tungsten burying process, the ferroelectric material is damaged greatly.
As shown in
FIG. 2
, there is a problem in combining an FRAM device and another device. A process of forming a ferroelectric capacitor having a stacked structure of a lower electrode
105
, ferroelectric film
106
and an upper electrode
107
in the FRAM device, is executed after the other device is done.
The biggest reason therefor is that the ferroelectric film
106
is weak in reduction atmosphere as described above. Accordingly, a step difference corresponding to the ferroelectric capacitor is caused between the devices, and it becomes difficult to form a wiring layer
109
on a step difference through contact holes of insulation film
108
of the lower layer and insulation film
108
′ of the upper layer.
As described above, the prior art semiconductor integrated circuit including an FRAM device has a drawback of making it difficult to achieve both a mixture of the FRAM device with another device and a high degree of integration.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed to resolve the above drawback, and its object is to provide a semiconductor integrated circuit having such a structure as to facilitate a high degree of integration and a mixture of two devices and to easily process an electrode and prevent a ferroelectric capacitor from being damaged.
To attain the above object, according to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a ferroelectric capacitor, the ferroelectric capacitor including:
a first insulation film formed above a semiconductor substrate;
a first electrode which is buried in a hole formed in the first insulation film and whose surface is flattened;
a second insulation film formed on the first insulation film and having an opening above the first electrode;
a ferroelectric film formed in the opening; and
a second electrode formed in the opening and above the ferroelectric film and flattened so as to be substantially flush with a surface of the second insulation film.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising a ferroelectric capacitor, the ferroelectric capacitor including:
a first insulation film formed above a semiconductor substrate;
a first electrode which is buried in a hole formed in the first insulation film;
a ferroelectric film which is formed in the hole and above the first electrode and whose surface is flattened;
a second insulation film formed on the first insulation film and having an opening above the ferroelectric film; and
a second electrode formed in the opening of the second insulation film.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising a ferroelectric capacitor, the ferroelectric capacitor including:
a first insulation film formed above a semiconductor substrate;
a first electrode which is buried in a hole formed in the first insulation film and whose surface is flattened;
a second insulation film formed on the first insulation film and having a first opening above the first electrode;
a ferroelectric film formed in the first opening and flattened so as to be substantially flush with a surface of the second insulation film;
a third insulation film formed on the second insulation film and having a second opening above the ferroelectric film; and
a second electrode formed in the second opening.
According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit, comprising the steps of:
forming a first insulation film whose surface is flattened, above a semiconductor substrate;
forming a first hole in the first insulation film;
depositing a first electrode film above the first insulation film and then flattening a surface of the first electrode film to form a first electrode in the first hole;
depositing a second insulation film above the. first electrode and the first insulation film;
forming a second hole in the second insulation film above the first electrode; and
depositing a ferroelectric film and a second electrode film in se
Hidaka Osamu
Kanaya Hiroyuki
Mochizuki Hiroshi
Okuwada Kumi
Cothorn Judith A.
Kabushiki Kaisha Toshiba
Wilczewski Mary
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