Semiconductor integrated circuit and layout method thereof

Details Semiconductor integrated circuit and layout method thereof Semiconductor integrated circuit and layout method thereof

1998-12-14

2000-10-10

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257773, 438129, H01L 2348, H01L 2352, H01L 2940

Patent

active

061304859

ABSTRACT:
A pad block is provided with a pad, an output buffer circuit and an internal circuit. The region between the internal circuit and the output buffer circuit serves as an element arrangement forbidden region. In this region, the internal circuit and the output buffer circuit are connected to each other by, for example, a polysilicon layer. The internal circuit is connected to a circuit formed in an internal region of a chip by using at least two wiring layers passing the element arrangement forbidden region. By laying out the wiring connecting the internal circuit within the pad block to the circuit in the internal region of the chip in the element arrangement forbidden region provided within the pad block, it is possible to reduce a space necessary for wiring and thereby to realize a highly integrated device.

REFERENCES:
patent: 5206529 (1993-04-01), Mine
patent: 5304826 (1994-04-01), Ichikawa et al.
patent: 5466956 (1995-11-01), Aeba
patent: 5665996 (1997-09-01), Williams et al.
patent: 5814893 (1998-09-01), Hsu et al.
patent: 5869870 (1999-02-01), Lin
patent: 5869900 (1999-02-01), Crafts

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