Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
Reexamination Certificate
2002-02-01
2003-10-21
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
Field-effect transistor
C326S101000, C326S103000, C326S033000, C326S034000
Reexamination Certificate
active
06636075
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit and its method of fabrication, particularly to a technique effectively applied to a semiconductor integrated circuit having a CMIS (Complementary Metal Insulator Semiconductor) for preventing thermal runaway during testing, as well as latch-up and fluctuation of the operation speed due to fluctuation of substrate potentials
BACKGROUND OF THE INVENTION
In recent years, various studies have been made of semiconductor integrated circuits in an effort to attain high integration, greater speed, and low power consumption. Particularly, in the case of a semiconductor integrated circuit having a MOS FET (Metal Oxide Semiconductor Field Effect Transistor) device, it has been necessary to further refine the sizes of devices and wirings in order to improve the degree of device integration and the operation speed and, therefore, the reduction in size of such semiconductor integrated circuits has progressed rapidly.
The present inventor has studied the scaling of a semiconductor integrated circuit. That is, scaling of a semiconductor integrated circuit, such as an LST (Large Scale Integrated circuit) includes two types of scaling—constant-voltage scaling and constant-electric-field scaling. In the case of a CMOS semiconductor integrated circuit including a CMOS FET as a component, constant-electric-field scaling is mainly employed for the purpose of securing the reliability of a gate oxide film. In this case, it is also necessary to lower the power supply voltage proportionally to effect reduction of the device size from the viewpoint of securing the stability of the device operating characteristic.
The literature on the fabrication of a CMOS semiconductor integrated circuit includes, for example, W. MALY “ZUSETSU CHO ERUESUAl KOCAKU (transliterated)”, pp. 167-191, issued by KEIGAKU SHUPPAN (transliterated) Co., Ltd. on Dec. 15, 1990. An original text of the above-transliterated publication is “Atlas of IC Technologies: An Introduction to VLSI Processes” by W. Maly (Copyright© 1987 by The Benjamin/Cummings Publishing Company Inc.).
In the case of the above-disclosed CMOS semiconductor integrated circuit, to make a scaling rule practically effective, it is necessary to lower the threshold voltage in proportion to the device size. This is because a voltage component contributing to the circuit operation can be represented by the expression “power supply voltage−threshold voltage”. However, because lowering of the threshold voltage causes an increase in leakage current, a leakage current test (I ddq test) widely used for testing a semiconductor integrated circuit cannot be performed, and, moreover, in the case of an aging test, the temperature is excessively raised due to an increase in the leakage current and, thereby, a problem of thermal runaway occurs.
FIG. 29
illustrates the mechanism of thermal runaway in the case of an aging test. In
FIG. 29
, the x-axis shows the set junction temperature (junction temperature Tj
1
) of a semiconductor integrated circuit and the y-axis shows the temperature (junction temperature Tj
2
) obtained by adding a temperature rise due to the total leakage current of a semiconductor integrated circuit produced due to the junction temperature Tj
1
increasing relative to the ambient temperature. Normally, the junction temperature Tj
2
and the junction temperature Tj
1
are stabilized at an equal temperature. However, when a leakage current component increases, the temperature is excessively raised due to the leakage current and, resultingly, thermal runaway occurs.
By applying a back bias to the well of a MOS FET in order to solve the above problem, it is possible to control the threshold voltage. In the case of this technique, however, the well potential may fluctuate due to noise under practical use (under normal operation) and a problem may occur in which a forward current is applied between the well and the source/drain to produce a so-called latch-up phenomenon.
One way of decreasing the leakage current by using a back bias is described in, for example, the official gazette of Japanese Patent Laid-Open No. 6-334010/1994, which discloses a structure in which the substrate node of a low-threshold-voltage field effect transistor, constituting a group of logic circuits, is connected to a power supply line, and a dummy power supply line, connected to the group of logic circuits, is connected to a power supply line through a high-threshold-voltage field effect transistor. In the case of this arrangement, the field effect transistor, whose substrate node is connected to the power supply line, can perform a normal operation at a low threshold voltage by turning on the high-threshold-voltage transistor under normal operation of the semiconductor integrated circuit, while the low-threshold-voltage field effect transistor can temporarily have a high threshold voltage by turning off the high-threshold-voltage field effect transistor and applying a test voltage to the dummy power supply line. However, this circuit has a problem in that the circuit impedance increases and, thereby, the general operation speed of the semiconductor integrated circuit lowers because the high-threshold-voltage field effect transistor is connected in series between the group of logic circuits and the power supply.
Moreover, the official gazette of Japanese Patent Laid-Open No 8-17183/1996 discloses a way of using switching means for making the substrate potential of a MOS FET variable as a means for controlling the threshold voltage of the MOS FET. This arrangement makes it possible to switch the switching characteristic and the sub-threshold current characteristic because the switching means switches the back gate bias of the MOS FET to a first potential or second potential and the absolute values of the threshold voltage of the MOS FET. In the case of this proposal, however, the source and n-well of a p-channel MOS FET are short-circuited each to the other through an n-channel MOS FET. Therefore, problems occur in that (1) it is necessary to generate a voltage higher than the power supply voltage under normal operation, and (2) the device characteristics are deteriorated because the high voltage in the above Item (1) is applied to the MOS FET and, thereby, the thickness of the gate oxide film of the MOS FET must be increased
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high-performance CMOS semiconductor integrated circuit which is capable of preventing the latch-up phenomenon, and its fabrication method.
Moreover, it is another object of the present invention to provide a way of preventing the latch-up phenomenon of a CMOS semiconductor integrated circuit from occurring under normal operation of the semiconductor integrated circuit and of preventing a leakage current from being generated during a test of the circuit.
Furthermore, it is still another object of the present invention to provide a way of improving the reliability of a CMOS semiconductor integrated circuit under normal operation and under test, without lowering the operation speed of the semiconductor integrated circuit under normal operation of the circuit. Furthermore, it is still another object of the present invention to provide a way of improving the reliability of a CMOS semiconductor integrated circuit under the normal operation and test of the circuit without deteriorating the device characteristics.
The above and other objects and novel features of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.
That is, a semiconductor integrated circuit of the present invention has a first power-supply-voltage line connected to a CMOS FET and a second power-supply-voltage line to which a voltage lower than that of the first power-supply-voltage line is applied, and moreover has a third power-supply-voltage line and a fourth power-supply-voltage line, independent of the first and the second power-supply-voltage lines, whi
Hamamoto Masato
Isomura Satoru
Mori Kazutaka
Nakayama Michiaki
Antonelli Terry Stout & Kraus LLP
Tran Anh
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