Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-04-25
2006-04-25
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
07036060
ABSTRACT:
A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.
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Hatayama Kazumi
Hikone Kazunori
Kobayashi Seiji
Nakao Michinobu
Shimamura Kotaro
Antonelli, Terry Stout and Kraus, LLP.
Hitachi , Ltd.
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