Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Reexamination Certificate
2006-11-09
2010-12-21
Whitmore, Stacy A (Department: 2825)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
C716S030000, C716S030000, C257S500000
Reexamination Certificate
active
07855579
ABSTRACT:
In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.
REFERENCES:
patent: 5648910 (1997-07-01), Ito
patent: 5972740 (1999-10-01), Nakamori
patent: 6477687 (2002-11-01), Thomas
patent: 6480989 (2002-11-01), Chan et al.
patent: 6687133 (2004-02-01), Liew et al.
patent: 6809419 (2004-10-01), Minami et al.
patent: 6868374 (2005-03-01), Ditlow et al.
patent: 6888395 (2005-05-01), Mizuno et al.
patent: 7129574 (2006-10-01), Wu
patent: 7199472 (2007-04-01), Minami et al.
patent: 7230477 (2007-06-01), Mizuno et al.
patent: 2004/0041268 (2004-03-01), Montagnana
patent: 2005/0160391 (2005-07-01), Orita
patent: 2005/0289494 (2005-12-01), Kozhaya et al.
patent: 7-283378 (1995-10-01), None
patent: 2003-318260 (2003-11-01), None
patent: 2004-111796 (2004-04-01), None
Fujiyama Kouji
Nagatani Takahiro
Takahashi Atsushi
McDermott Will & Emery LLP
Panasonic Corporation
Whitmore Stacy A
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