Semiconductor integrated circuit and BIST circuit design method

Details Semiconductor integrated circuit and BIST circuit design method Semiconductor integrated circuit and BIST circuit design method

2007-04-02

2009-11-17

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07620869

ABSTRACT:
A semiconductor integrated circuit comprising a plurality of memory circuits; a BSIT circuit140operable to output test vectors; and one or more register circuit(s)150each allocated on a signal line that transmits test vectors output by the BIST circuit140to any of the memory circuits, and operable to sequentially transfer the test vectors to an adjoining macro cell in accordance with the clock signals.

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